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| ? 2013 microchip technology inc. preliminary ds40001684b-page 1 PIC16F570 processor features: ? interrupt capability ? PIC16F570 operating speed: - dc ? 20 mhz crystal oscillator - dc ? 200 ns instruction cycle ? high endurance program and flash data memory cells: - 2048 x 12 user execution memory - 64 x 8 self-writable data memory - 100,000 write program memory endurance - 1,000.000 write flash data memory endurance - program and flash data retention: >40 years ? general purpose registers (sram): - 132 x 8 memory ? only 36 single-word instructions to learn: - modified baseline cpu - added return and retfie instructions - added movlb instruction ? all instructions are single-cycle except for program branches which are two-cycle ? four-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions peripheral features: ? device features: - 24 i/os - individual direction control - high-current source/sink ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler ? in-circuit serial programming? (icsp?) via two external pin connections ? analog comparator (cmp): - two analog comparators - absolute and programmable references ? analog-to-digital converter (adc): - 8-bit resolution - eight external input channels - 0.6v reference input ? operational amplifiers (op amps): - two operational amplifiers - fully-accessible visibility microcontroller features: ? brown-out reset (bor) ? power-on reset (por) ? device reset timer (drt) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection (cp) ? power-saving sleep mode with wake-up on change feature ? selectable oscillator options: - intosc: precision 4 or 8 mhz internal oscillator - extrc: low-cost external rc oscillator - lp: power-saving, low-frequency crystal - xt: standard crystal/resonator - hs: high-speed crystal/resonator - ec: high-speed external clock ? variety of packaging options: - 28-lead spdip, soic, ssop, qfn, uqfn cmos technology: ? low-power, high-speed cmos flash technology ? fully-static design ? wide operating voltage and temperature range: - industrial: 2.0v to 5.5v - extended: 2.0v to 5.5v ? operating current: - 175 ua @ 2v, 4 mhz, typical - 13 ua @ 2v, 32 khz, typical ? standby current: - 100 na @ 2v, typical 28-pin, 8-bit flas h microcontroller
PIC16F570 ds40001684b-page 2 preliminary ? 2013 microchip technology inc. figure 1: 28-pin diagram for PIC16F570 figure 2: 28-pin diagram for PIC16F570 table 1: pic16f527 and PIC16F570 family types device data sheet index i/o pins (1) flash data ee (b) sram (b) 8-bit adc channels op amp comparator 8-bit timers bor stack levels interrupts 8 mhz int. osc. interrupt-on-change pins weak pull-up pins pic16f527 (1) 18 1 kw 64 68 8 2 2 1 y 4 y y 4 4 PIC16F570 (2) 25 2 kw 64 132 8 2 2 1 y 4 y y 8 8 note 1: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: ds41652 pic16f527 data sheet, 20-pin, 8-bit flash microcontroller. 2: ds40001684 PIC16F570 data sheet, 28-pin, 8-bit flash microcontroller. spdip, ssop, soic PIC16F570 1 2 3 4 5 6 7 14 15 16 17 18 19 20 8 9 10 11 12 13 mclr /v pp ra0 ra1 ra2 ra3 ra4 ra5 v ss ra7 ra6 rc0 rc1 rc2 rc3 23 24 25 26 27 28 21 22 rb7/icspdat rb6/icspclk rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 PIC16F570 2 3 6 1 18 19 20 21 15 7 16 17 rc0 5 4 rb7/icspdat rb6/icspclk rb5 rb4 rb0 v dd v ss rc7 rc6 rc5 rc4 m clr /v pp ra0 ra1 ra2 ra3 ra4 ra5 v ss ra7 ra6 rc1 rc2 rc3 9 10 13 8 14 12 11 27 26 23 28 22 24 25 rb3 rb2 rb1 qfn, uqfn ? 2013 microchip technology inc. preliminary ds40001684b-page 3 PIC16F570 table 2: 28-pin allocation table i/o 28-pin spdip, ssop, soic 28-pin qfn, uqfn adc reference comparator op amp timers interrupt-on-change pull-up basic mclr 126 ? ? ? ? ? ny mclr v pp ra0 2 27 an0 ? ? ? n n ? ra1 3 28 an1 ? c1in+ ? ? n n ? ra2 4 1 an2 cv ref 1 ? ? ? n n ? ra3 5 2 an3 ? c2in+ ? ? n n ? ra4 6 3 an4 ? ? ? t0cki n n ? ra5 7 4 an5 ? ? ? ? n n ? ra6 10 7 ? ? ? ? ? n n osc2 clkout ra7 9 6 ? ? ? ? ? n n osc1 clkin rb0 21 18 ? ? ? ? ? y y ? rb1 22 19 ? ? ? ? ? y y ? rb2 23 20 ? ? ? ? ? y y ? rb3 24 21 ? ? c1out ? ? y y ? rb4 25 22 ? ? c2out ? ? y y ? rb5 26 23 ? ? ? ? ? y y ? rb6 27 24 ? ? ? ? ? y y icspclk rb7 28 25 ? cv ref 2 c1in- ? ? y y icspdat rc0 11 8 ? ? ? ? ? n n ? rc1 12 9 an6 ? ? op1 ? n n ? rc2 13 10 ? ? ? op1- ? n n ? rc3 14 11 ? ? ? op1+ ? n n ? rc4 15 12 ? ? ? op2+ ? n n ? rc5 16 13 ? ? ? op2- ? n n ? rc6 17 14 an7 ? ? op2 ? n n ? rc7 18 15 ? ? c2in- ? ? n n ? v dd 20 17 ? ? ? ? ? ? ? v dd vss 8, 19 5, 16 ?? ? ? ???v ss PIC16F570 ds40001684b-page 4 preliminary ? 2013 microchip technology inc. table of contents 1.0 general description......................................................................................................... ............................................................ 5 2.0 PIC16F570 device varieties .................................................................................... .............. .................................................... 8 3.0 architectural overview ...................................................................................................... ........................................................ 10 4.0 memory organization ......................................................................................................... ....................................................... 16 5.0 self-writable flash data memory control ..................................................................................... ............................................ 28 6.0 i/o port .................................................................................................................... .................................................................. 32 7.0 timer0 module and tmr0 register ............................................................................................. ............................................. 38 8.0 special features of the cpu ................................................................................................. .................................................... 44 9.0 analog-to-digital (a/d) converter........................................................................................... ................................................... 62 10.0 comparator(s) .............................................................................................................. ............................................................. 68 11.0 comparator voltage reference module ........................................................................................ ............................................ 74 12.0 operational amplifier (opa) module ......................................................................................... ................................................ 76 13.0 instruction set summary .................................................................................................... ....................................................... 78 14.0 development support........................................................................................................ ........................................................ 87 15.0 electrical characteristics ................................................................................................. .......................................................... 91 16.0 dc and ac characteristics graphs and charts ................................................................................ ...................................... 109 17.0 packaging information...................................................................................................... ....................................................... 111 index .......................................................................................................................... ........................................................................ 127 the microchip web site ......................................................................................................... ........................................................... 129 customer change notification service ........................................................................................... .................................................. 129 customer support ............................................................................................................... .............................................................. 129 reader response ................................................................................................................ ............................................................. 130 product identification system.................................................................................................. .......................................................... 131 to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. ? 2013 microchip technology inc. preliminary ds40001684b-page 5 PIC16F570 1.0 general description the PIC16F570 device from microchip technology is a low-cost, high-performance, 8-bit, fully-static, flash- based cmos microcontroller. it employs a risc architecture with only 36 single-word/single-cycle instructions. all instructions are single cycle except for program branches, which take two cycles. the PIC16F570 device delivers performance an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy-to-use and easy to remember instruction set reduces development time significantly. the PIC16F570 product is equipped with special features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are several oscillator configurations to choose from, including intrc internal oscillator mode and the power-saving lp (low-power) oscillator mode. power-saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the PIC16F570 device is available in the cost-effective flash programmable version, which is suitable for production in any volume. the customer can take full advantage of microchip?s price leadership in flash programmable microcontrollers, while benefiting from the flash programmable flexibility. the PIC16F570 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ?c? compiler, a low-cost development programmer and a full-featured programmer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the PIC16F570 device fits in applications ranging from personal care appliances and security systems to low- power remote transmitters/receivers. the flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the PIC16F570 device very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and plds in larger systems and co-processor applications). table 1-1: features and memory of PIC16F570 PIC16F570 clock maximum frequency of operation (mhz) 20 memory flash program memory 2048 sram data memory (bytes) 132 flash data memory (bytes) 64 peripherals timer module(s) tmr0 wake-up from sleep on pin change yes features i/o pins 24 input pins 1 internal pull-ups yes in-circuit serial programming tm yes number of instructions 36 packages 28-pin spdip, soic, ssop, qfn, uqfn PIC16F570 ds40001684b-page 6 preliminary ? 2013 microchip technology inc. the PIC16F570 device has power-on reset, selectable watchdog timer, selectable code-protect, high i/o current capability and precision internal oscillator. the PIC16F570 device uses serial programming with the icspdat data pin and the icspclk clock pin. ? 2013 microchip technology inc. preliminary ds40001684b-page 7 PIC16F570 notes: PIC16F570 ds40001684b-page 8 preliminary ? 2013 microchip technology inc. 2.0 PIC16F570 device varieties a variety of packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the PIC16F570 product identification system at the back of this data sheet to specify the correct part number. 2.1 quick turn programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. the devices are identical to the flash devices but with all flash locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.2 serialized quick turn programming sm (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry code, password or id number. ? 2013 microchip technology inc. preliminary ds40001684b-page 9 PIC16F570 notes: PIC16F570 ds40001684b-page 10 preliminary ? 2013 microchip technology inc. 3.0 architectural overview the high performance of the PIC16F570 device can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the PIC16F570 device uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architectures where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions execute in a single cycle (200 ns @ 20 mhz, 1 ? s @ 4 mhz) except for program branches. table 3-1 below lists memory supported by the PIC16F570 device. table 3-1: PIC16F570 memory the PIC16F570 device can directly or indirectly address its register files and data memory. all special function registers (sfr), including the pc, are mapped in the data memory. the PIC16F570 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. this sym- metrical nature and lack of ?special optimal situations? make programming with the PIC16F570 device simple, yet efficient. in addition, the learning curve is reduced significantly. the PIC16F570 device contains an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. unless otherwise mentioned, arithmetic operations are two?s comple- ment in nature. in two-operand instructions, one operand is typically the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc) and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-2 , with the corresponding device pins described in tab l e 3 - 2 . device program memory data memory flash (words) sram (bytes) flash (bytes) PIC16F570 2048 132 64 ? 2013 microchip technology inc. preliminary ds40001684b-page 11 PIC16F570 figure 3-1: pic16f 570 block diagram flash program memory 11 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 0-4 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg device reset power-on reset watchdog timer instruction decode and control timing generation osc1/clkin osc2/clkout mclr /v pp v dd , v ss timer0 porta 8 8 ra4 ra3 ra2 ra1 ra0 0-7 3 ra5 stack1 stack2 132 internal rc clock 2k x 12 bytes timer portc rc4 rc3 rc2 rc1 rc0 rc5 comparator 2 c1in+ c1in- c1out c2in+ c2in- c2out an5 an6 an7 v ref 8-bit adc cv ref 1 cv ref self-write 64x8 v ref comparator 1 stack3 stack4 brown-out reset portb rb3 rb2 rb1 rb0 rc7 rc6 t0cki opamp1 and opamp2 op2- op2 op1+ op1- op1 op2+ an0 an1 an2 an3 an4 direct addr bsr 5-7 3 rb5 rb4 ra6 ra7 rb7/icspdat rb6/icspclk cv ref 2 PIC16F570 ds40001684b-page 12 preliminary ? 2013 microchip technology inc. table 3-2: PIC16F570 pinout description name function input type output type description v pp /mclr v pp hv ? test mode high-voltage pin mclr st ? master clear (reset). this pin is an active-low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. weak pull-up is always on. ra0/an0 ra0 ttl cmos bidirectional i/o pin an0 an ? adc channel input ra1/an1/c1in+ ra1 ttl cmos bidirectional i/o pin an1 an ? adc channel input c1in+ an ? comparator 1 non-inverting input ra2/an2/cv ref 1 ra2 ttl cmos bidirectional i/o port an2 an ? adc channel input cv ref 1 ? an programmable voltage reference output 1 ra3/an3/c2in+ ra3 ttl cmos bidirectional i/o pin an3 an ? adc channel input c2in+ an ? comparator 2 non-inverting input ra4/an4/t0cki ra4 ttl cmos bidirectional i/o pin an4 an ? adc channel input t0cki st ? timer0 schmitt trigger input pin ra5/an5 ra5 ttl cmos bidirectional i/o port an5 an ? adc channel input ra7/clkin/osc1 ra7 ttl cmos bidirectional i/o port clkin st ? extrc schmitt trigger input osc1 xtal ? xtal oscillator input pin ra6/clkout/osc2 ra6 ttl cmos bidirectional i/o port clkout ? cmos extrc/intrc clkout pin (f osc /4) osc2 ? xtal oscillator crystal output. connections to crystal or resonator in crystal oscillator mode (xt, hs and lp modes only, portb in other modes). rc0 rc0 st cmos bidirectional i/o port rc1/an6/op1 rc1 st cmos bidirectional i/o port an6 an ? adc channel input op1 ? an op amp 1 output rc2/op1- rc2 st cmos bidirectional i/o port op1- an ? op amp 1 inverting input rc3/op1+ rc3 st cmos bidirectional i/o port op1+ an ? op amp 1 non-inverting input rc4/op2+ rc4 st cmos bidirectional i/o port op2+ an ? op amp 2 non-inverting input rc5/op2- rc5 st cmos bidirectional i/o port op2- an ? op amp 2 inverting input rc6/an7/op2 rc6 st cmos bidirectional i/o port an7 an ? adc channel input op2 ? an op amp 2 output legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, hv = high voltage, an = analog voltage ? 2013 microchip technology inc. preliminary ds40001684b-page 13 PIC16F570 rc7/c2in- rc7 st cmos bidirectional i/o port c2in- an ? comparator 2 inverting input rb0 rb0 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. rb1 rb1 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. rb2 rb2 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. rb3/c1out rb3 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. c1out ? cmos comparator 1 output rb4/c2out rb4 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. c2out ? cmos comparator 2 output rb5 rb5 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. rb6/icspclk rb6 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspclk st ? icsp? mode schmitt trigger rb7/icspdat/c1in-/ cv ref 2 rb7 ttl cmos bidirectional i/o pin. it can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspdat st cmos icsp? mode schmitt trigger c1in- an ? comparator 1 inverting input cv ref 2 ? an programmable voltage reference output 2 v dd v dd ? p positive supply for logic and i/o pins v ss v ss ? p ground reference for logic and i/o pins table 3-2: PIC16F570 pinout description name function input type output type description legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, hv = high voltage, an = analog voltage PIC16F570 ds40001684b-page 14 preliminary ? 2013 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pc is incremented every q1 and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1 . 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the pc to change (e.g., goto or an interrupt), then two cycles are required to complete the instruction ( example 3-1 ). a fetch cycle begins with the pc incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc + 1 pc + 2 fetch inst (pc) execute inst (pc ? 1) fetch inst (pc + 1) execute inst (pc) fetch inst (pc + 2) execute inst (pc + 1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf portb, bit1 fetch 4 flush fetch sub_1 execute sub_1 ? 2013 microchip technology inc. preliminary ds40001684b-page 15 PIC16F570 notes: PIC16F570 ds40001684b-page 16 preliminary ? 2013 microchip technology inc. 4.0 memory organization the PIC16F570 memories are organized into program memory and data memory (sram).the self-writable portion of the program memory called self-writable flash data memory is located at addresses 800h-83fh. all program mode commands that work on the normal flash memory, work on the flash data memory. this includes bulk erase, row/column/cycling toggles, load and read data commands (refer to section 5.0 ?self- writable flash data memory control? for more details). for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one status register bit. for the PIC16F570, with data memory register files of more than 32 registers, a banking scheme is used. data memory banks are accessed directly using the bank select register (bsr). 4.1 program memory organization for PIC16F570 the PIC16F570 device has an 11-bit program counter (pc) capable of addressing a 2k x 12 program memory space. program memory is partitioned into user memory, data memory and configuration memory spaces. the user memory space is the on-chip user program memory. as shown in figure 4-1 , it extends from 0x000 to 0x7ff and partitions into pages, including an interrupt vector at address 0x004 and a reset vector at address 0x7ff. the configuration memory space extends from 0x840 to 0xfff. locations from 0x848 through 0x8af are reserved. the user id locations extend from 0x840 through 0x843. the backup osccal locations extend from 0x844 through 0x847. the configuration word is physically located at 0xfff. refer to ? PIC16F570 memory programming specification ? (ds41670) for more details. figure 4-1: memory map 000h 1ffh reset vector on-chip user program memory (page 0) 200h 7ffh 7feh user id locations reserved configuration word 800h 843h 844h ffeh fffh 83fh 840h unimplemented on-chip user program memory (page 1) data memory self-writable 848h 8afh backup osccal locations 847h 8b0h configuration memory space space user memory space flash data memory on-chip user program memory (page 2) on-chip user program memory (page 3) 3ffh 400h 5ffh 600h ? 2013 microchip technology inc. preliminary ds40001684b-page 17 PIC16F570 4.2 data memory (sram and sfrs) data memory is composed of registers or bytes of sram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers (sfr) and general purpose registers (gpr). the special function registers are registers used by the cpu and peripheral functions for controlling desired operations of the PIC16F570. see section 4.3 ?status register? for details. 4.2.1 general purpose register file the general purpose register file is accessed directly or indirectly. see section 4.8 ?direct and indirect addressing? . 4.2.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device ( section 4.3 ?status register? ). the special function registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. PIC16F570 ds40001684b-page 18 preliminary ? 2013 microchip technology inc. figure 4-2: PIC16F570 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal porta 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 5fh 50h 40h 7fh 70h 60h general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers portb 08h note 1: not a physical register. see section 4.8 ?direct and indirect addressing? . bsr<2:0> 000 001 010 011 2fh 4fh 6fh portc intcon0 09h 0ah 0bh adres adcon0 0ch 0fh indf (1) eecon pcl status fsr eedata eeadr cm2con0 intcon0 ansel vrcon indf (1) tmr0 pcl status fsr osccal porta portb adres adcon0 indf (1) iw pcl status fsr intcon1 istatus ansel opacon portc ibsr intcon0 intcon0 addresses map back to addresses in bank 0. cm1con0 ifsr indf (1) tmr0 pcl status fsr osccal porta bank 4 bank 5 bank 6 bank 7 bfh b0h a0h dfh d0h c0h ffh f0h e0h general purpose registers general purpose registers general purpose registers general purpose registers portb 100 101 110 111 afh cfh efh portc intcon0 adres adcon0 indf (1) eecon pcl status fsr eedata eeadr cm2con0 intcon0 ansel vrcon indf (1) tmr0 pcl status fsr osccal porta portb adres adcon0 indf (1) iw pcl status fsr intcon1 istatus ansel opacon portc ibsr intcon0 intcon0 cm1con0 ifsr 8fh 90h 9fh 80h ? 2013 microchip technology inc. preliminary ds40001684b-page 19 PIC16F570 table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por/bor value on all other resets bank 0/4 n/a w (2) working register (w) xxxx xxxx xxxx xxxx n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 1111 1111 n/a bsr (2) ? ? ? ? ? bsr2 bsr1 bsr0 ---- -000 ---- -uuu 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h tmr0 timer0 module register xxxx xxxx uuuu uuuu 02h pcl (1) low-order eight bits of pc 1111 1111 1111 1111 03h status (2) pa2 pa1 pa0 to pd zdcc 0001 1xxx 000q qqqq 04h fsr (2) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- uuuu uuu- 06h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx xxxx uuuu uuuu 07h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 08h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 09h adcon0 adcs1 adcs0 chs3 chs2 chs1 chs0 go/done adon 1111 1100 1111 1100 0ah adres adc conversion result xxxx xxxx uuuu uuuu 0bh intcon0 adif cwif t0if rbif ? ? ? gie 0000 ---0 0000 ---0 bank 1/5 n/a w (2) working register (w) xxxx xxxx xxxx xxxx n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 1111 1111 n/a bsr (2) ? ? ? ? ? bsr2 bsr1 bsr0 ---- -000 ---- -uuu 20h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 21h eecon ? ? ? free wrerr wren wr rd ---0 0000 ---0 0000 22h pcl (1) low-order eight bits of pc 1111 1111 1111 1111 23h status (2) pa2 pa1 pa0 to pd zdcc 0001 1xxx 000q qqqq 24h fsr (2) indirect data memory address pointer xxxx xxxx uuuu uuuu 25h eedata self read/write data xxxx xxxx uuuu uuuu 26h eeadr ? ? self read/write address --xx xxxx --uu uuuu 27h cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 quuu uuuu 28h cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 1111 1111 quuu uuuu 29h vrcon vren vroe1 vroe2 vrr vr3 vr2 vr1 vr0 0001 1111 uuuu uuuu 2ah ansel ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 2bh intcon0 adif cwif t0if rbif ? ? ? gie 0000 ---0 0000 ---0 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ? (if applicable), q = value depends on condition. shaded cells = unimplemented or unused note 1: the upper byte of the program counter is not directly accessible. see section 4.6 ?program counter? for an explanation of how to access these bits. 2: registers are implemented as two physical registers. when executing from within an isr, a secondary register is used at the sam e logical location. both registers are persistent. see section 8.11 ?interrupts? . 3: these registers show the contents of the registers in the other context: isr or main line code. see section 8.11 ?interrupts? . PIC16F570 ds40001684b-page 20 preliminary ? 2013 microchip technology inc. bank 2/6 n/a w (2) working register (w) xxxx xxxx xxxx xxxx n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 1111 1111 n/a bsr (2) ? ? ? ? ? bsr2 bsr1 bsr0 ---- -000 ---- -uuu 40h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 41h tmr0 timer0 module register xxxx xxxx uuuu uuuu 42h pcl (1) low-order eight bits of pc 1111 1111 1111 1111 43h status (2) pa2 pa1 pa0 to pd zdcc 0001 1xxx 000q qqqq 44h fsr (2) indirect data memory address pointer xxxx xxxx uuuu uuuu 45h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- uuuu uuu- 46h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx xxxx uuuu uuuu 47h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 48h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 49h adcon0 adcs1 adcs0 chs3 chs2 chs1 chs0 go/done adon 1111 1100 1111 1100 4ah adres adc conversion result xxxx xxxx uuuu uuuu 4bh intcon0 adif cwif t0if rbif ? ? ? gie 0000 ---0 0000 ---0 bank 3/7 n/a w (2) working register (w) xxxx xxxx xxxx xxxx n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 1111 1111 n/a bsr (2) ? ? ? ? ? bsr2 bsr1 bsr0 ---- -000 ---- -0uu 60h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 61h iw (3) interrupt working register. (addressed also as w register when within isr) xxxx xxxx xxxx xxxx 62h pcl (1) low-order eight bits of pc 1111 1111 1111 1111 63h status (2) pa2 pa1 pa0 to pd zdcc 0001 1xxx 000q qqqq 64h fsr (2) indirect data memory address pointer xxxx xxxx uuuu uuuu 65h intcon1 adie cwie t0ie rbie ? ? ? wur 0000 ---0 0000 ---0 66h istatus (3) pa2 pa1 pa0 to pd zdcc xxxx xxxx 000q qqqq 67h ifsr (3) ? indirect data memory address pointer 0xxx xxxx 0uuu uuuu 68h ibsr (3) ? ? ? ? ? bsr2 bsr1 bsr0 ---- -xxx ---- -uuu 69h opacon ? ? ? ? ? ? opa2on opa1on ---- --00 ---- --00 6bh intcon0 adif cwif t0if rbif ? ? ? gie 0000 ---0 0000 ---0 table 4-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por/bor value on all other resets legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ? (if applicable), q = value depends on condition. shaded cells = unimplemented or unused note 1: the upper byte of the program counter is not directly accessible. see section 4.6 ?program counter? for an explanation of how to access these bits. 2: registers are implemented as two physical registers. when executing from within an isr, a secondary register is used at the sam e logical location. both registers are persistent. see section 8.11 ?interrupts? . 3: these registers show the contents of the registers in the other context: isr or main line code. see section 8.11 ?interrupts? . ? 2013 microchip technology inc. preliminary ds40001684b-page 21 PIC16F570 4.3 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status, will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). therefore, it is recommended that only bcf , bsf and movwf instructions be used to alter the status register. these instructions do not affect the z, dc or c bits from the status register. for other instructions which do affect status bits, see section 13.0 ?instruction set summary? . register 4-1: status: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x pa2 pa1 pa0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 pa<2:0> : program page preselect bits x00 = page 0 (000h-1ffh) x01 = page 1 (200h-3ffh) x10 = page 2 (400h-5ffh) x11 = page 3 (600h-7ffh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf: subwf: rrf or rlf: 1 = a carry occurred 1 = a borrow did not occur; load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred PIC16F570 ds40001684b-page 22 preliminary ? 2013 microchip technology inc. 4.4 option register the option register is an 8-bit wide, write-only regis- ter, which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option <7:0> bits. note: if tris bit is set to ? 0 ?, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of r bp u and r bw u ). register 4-2: option: option register w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 r bw u (2) r bp u t0cs (1) t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 r bw u : enable portb interrupt flag on pin change bit (2) 1 = disabled 0 = enabled bit 6 r bp u : enable portb weak pull-ups bit 1 = disabled 0 = enabled bit 5 t0cs: timer0 clock source select bit (1) 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits note 1: if the t0cs bit is set to ? 1 ?, it will override the tris function on the t0cki pin. 2: the r bw u bit of the option register must be set to enable the rbif function in the intcon0 register. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate ? 2013 microchip technology inc. preliminary ds40001684b-page 23 PIC16F570 4.5 osccal register the oscillator calibration (osccal) register is used to calibrate the 8 mhz internal oscillator macro. it contains seven bits of calibration that uses a two?s complement scheme for controlling the oscillator speed. see register 4-3 for details. register 4-3: osccal: osci llator calibration register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 cal<6:0> : oscillator calibration bits 0111111 = maximum frequency ? ? ? 0000001 0000000 = center frequency 1111111 ? ? ? 1000000 = minimum frequency bit 0 unimplemented : read as ? 0 ? PIC16F570 ds40001684b-page 24 preliminary ? 2013 microchip technology inc. 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits <8:0> of the pc are provided by the goto instruction word. the program counter (pcl) is mapped to pc<7:0>. bits 5 and 6 of the status register provide page information to bits 9 and 10 of the pc ( figure 4-3 ). for a call instruction, or any instruction where the pcl is the destination, bits <7:0> of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared ( figure 4-3 ). instructions where the pcl is the destination, or modify pcl instructions, include movwf pcl, addwf pcl and bsf pcl,5. figure 4-3: loading of pc branch instructions 4.6.1 effects of reset the pc is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the oscillator calibration instruction). after executing movlw xx , the pc will roll over to location 00h and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre-selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 stack the PIC16F570 device has a 4-deep, 12-bit wide hardware push/pop stack. a call instruction or an interrupt will push the current pc value, incremented by one, into stack level 1. if there was a previous value in the stack 1 location, it will be pushed into the stack 2 location. this process will be continued throughout the remaining stack locations pop- ulated with values. if more than four sequential call s are executed, only the most recent four return addresses are stored. a retlw, return or retfie instruction will pop the contents of stack level 1 into the pc. if there was a previous value in the stack 2 location, it will be copied into the stack level 1 location. this process will be con- tinued throughout the remaining stack locations popu- lated with values. if more than four sequential retlw s are executed, the stack will be filled with the address previously stored in stack level 4. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. note: because bit 8 of the pc is cleared in the call instruction or any modify pcl instruction, all subroutine calls or com- puted jumps are limited to the first 256 locations of any program memory page (512 words long). pa0 status pc 87 0 pcl 9 10 instruction word 7 0 goto instruction call or modify pcl instruction pa0 status pc 87 0 pcl 9 10 instruction word 7 0 reset to ? 0 ? pa1 pa1 note 1: there are no status bits to indicate stack overflows or stack underflow conditions. 2: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call, return, retfie and retlw instructions. ? 2013 microchip technology inc. preliminary ds40001684b-page 25 PIC16F570 4.8 direct and indirect addressing 4.8.1 direct data addressing: bsr register traditional data memory addressing is performed in the direct addressing mode. in direct addressing, the bank select register bits bsr<2:0>, in the new bsr register, are used to select the data memory bank. the address location within that bank comes directly from the opcode being executed. bsr<2:0> are the bank select bits and are used to select the bank to be addressed ( 000 = bank 0, 001 = bank 1, 010 = bank 2, 011 = bank 3, 100 = bank 4, etc.). a new instruction supports the addition of the bsr register, called the movlb instruction. see section 13.0 ?instruction set summary? for more information. 4.8.2 indirect data addressing: indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. reading indf itself indirectly (fsr = 0 ) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). the fsr is an 8-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<7:0> bits are used to select data memory addresses 00h to 1fh. a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-1 . example 4-1: how to clear ram using indirect addressing movlw 0x10 ;initialize p ointer movwf fsr ;to ram next clrf indf ;clear indf ;register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : PIC16F570 ds40001684b-page 26 preliminary ? 2013 microchip technology inc. figure 4-4: direct/indirect addressing location select location select bank select indirect addressing direct addressing 0 4 5 6 (fsr) (opcode) 0 4 0 1 (bsr) 3 2 1 3 2 1 7 2 note 1: for register map detail see figure 4-2 . data memory (1) 0bh 0ch 000 001 111 00h 0fh 2fh efh 10h bank 0 bank 1 bank 7 1fh 3fh ffh addresses map back to addresses in bank 0. 20h 2bh e0h ebh ech 2ch 30h f0h ? 2013 microchip technology inc. preliminary ds40001684b-page 27 PIC16F570 notes: PIC16F570 ds40001684b-page 28 preliminary ? 2013 microchip technology inc. 5.0 self-writable flash data memory control flash data memory consists of 64 bytes of self- writable memory and supports a self-write capability that can write four bytes of memory at one time. data to be written to the self-writable data memory is first written into four write latches before writing the data to flash memory. although each flash data memory location is 12 bits wide, access is limited to the lower eight bits. the upper four bits will automatically default to ? 1 ? in any self-write procedure. the lower eight bits are fully readable and writable during normal operation and throughout the full v dd range. the self-writable flash data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers, eecon, eedata and eeadr. 5.1 reading flash data memory to read a flash data memory location the user must: ? write the eeadr register ? set the rd bit of the eecon register the value written to the eeadr register determines which flash data memory location is read. setting the rd bit of the eecon register initiates the read. data from the flash data memory read is available in the eedata register immediately. the eedata register will hold this value until another read is initiated or it is modified by a write operation. program execution is suspended while the read cycle is in progress. execution will continue with the instruction following the one that sets the wr bit. see example 5-1 for sample code. example 5-1: reading from flash data memory 5.1.1 erasing flash data memory a row must be manually erased before writing new data. the following sequence must be performed for a single row erase. 1. load eeadr with an address in the row to be erased. 2. set the free bit to enable the erase. 3. set the wren bit to enable write access to the array. 4. disable interrupts. 5. set the wr bit to initiate the erase cycle. if the wren bit is not set in the instruction cycle after the free bit is set, the free bit will be cleared in hardware. if the wr bit is not set in the instruction cycle after the wren bit is set, the wren bit will be cleared in hardware. sample code that follows this procedure is included in example 5-2 . program execution is suspended while the erase cycle is in progress. execution will continue with the instruction following the one that sets the wr bit. example 5-2: erasing a flash data memory row note: only a bsf command will work to enable the flash data memory read documented in example 5-1 . no other sequence of commands will work, no exceptions. movlb 0x01 ; switch to bank 1 movf data_ee_addr,w ; movwf eeadr ; data memory ; address to read bsf eecon, rd ; ee read movf eedata, w ; w = eedata note 1: to prevent accidental corruption of the flash data memory, an unlock sequence is required to initiate a write or erase cycle. this sequence requires that the bit set instructions used to configure the eecon register happen exactly as shown in example 5-2 and example 5-3 , depending on the operation requested. 2: in order to prevent any disruptions of self- writes or row erases performed on the self-writable flash data memory, interrupts should be disabled prior to executing those routines. movlb 0x01 ; switch to bank 1 movlw ee_adr_erase ; load address of row to ; erase movwf eeadr ; bsf eecon,free ; select erase bsf eecon,wren ; enable writes bsf eecon,wr ; inititate erase ? 2013 microchip technology inc. preliminary ds40001684b-page 29 PIC16F570 5.1.2 writing to flash data memory once a cell is erased, new data can be written. program execution is suspended during the write cycle. the self-write operation writes four bytes of data at one time. the data must first be loaded into four write latches. once the write latches are loaded, the data will be written to flash data memory. the self-write sequence is shown below. the following self-write sequence must be performed for four bytes to be written. 1. load eeadr with the address. 2. load eedata with the data to be written. 3. set the wren bit to enable write access to the array. 4. disable interrupts. 5. set the wr bit to load the data into the write latch. 6. steps 1 through 5 are repeated three more times to load the remaining write latches. on the fourth and final loop, the eeadr register will contain an address in the format of b?00xxxx11 . when the wr bit is set for the final time, the processor will recognize that this is the last write latch to be loaded, and will automatically load the write latch and then, immediately perform the flash data memory write of all four bytes. the specific sequence of setting the wren bit and setting the wr bit must be executed to properly initiate each load of the write latches and the write to flash data memory. if the wr bit is not set in the instruction cycle after the wren bit is set, the wren bit will be cleared in hardware. sample code that follows this procedure is included in example 5-3 . example 5-3: writing to flash data memory 5.2 write/verify depending on the application, good programming practice may dictate that data written to the flash data memory be verified. example 5-4 is an example of a write/verify. example 5-4: write/verify of flash data memory note 1: the free bit may be set by any command normally used by the core. however, the wren and wr bits can only be set using a series of bsf com- mands, as documented in example 5-1 . no other sequence of commands will work, no exceptions. 2: bits <5:3> of the eeadr register indicate which row is to be erased. note 1: only a series of bsf commands will work to enable the memory write sequence documented in example 5-3 . no other sequence of commands will work, no exceptions. 2: for reads, erases and writes to the flash data memory, there is no need to insert a nop into the user code as is done on mid- range devices. the instruction immediately following the ? bsf eecon,wr/rd ? will be fetched and executed properly. movlb 0x01 ;switch to bank 1 movlw 0x04 ;load 4 data bytes movwf loopcount ;write loop write_loop ;variable stored movlw ee_adr_write ;load address to ;write movwf eeadr ;into eeadr ;register movlw ee_data_to_write;load data to movwf eedata ;into eedata ;register bsf eecon,wren ;enable writes bsf eecon,wr ;load write latch btfsc loopcount ;test if 4th byte goto write_loop ; ;write is done ; movf eedata, w ;eedata has not changed ;from previous write bsf eecon, rd ;read the value written xorwf eedata, w ; btfss status, z ;is data the same goto write_err ;no, handle error ;yes, continue PIC16F570 ds40001684b-page 30 preliminary ? 2013 microchip technology inc. 5.3 register definitions ? memory control register 5-1: eedata: flash data register register 5-2: eeadr: flash address register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eedata7 eedata6 eedata5 eedata4 eedata3 eedata2 eedata1 eedata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 eedata<7:0> : eight bits of data to be read from/written to data flash u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ?. bit 5-0 eeadr<5:0> : six bits of data to be read from/written to data flash ? 2013 microchip technology inc. preliminary ds40001684b-page 31 PIC16F570 register 5-3: eecon: flash control register 5.4 code protection code protection does not prevent the cpu from performing read or write operations on the flash data memory. refer to the code protection chapter for more information. u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? free wrerr wren wr rd bit 7 bit 0 legend: s = bit can only be set r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ?. bit 4 free: flash data memory row erase enable bit 1 = program memory row being pointed to by eeadr will be erased on the next write cycle. no write will be performed. this bit is cleared at the completion of the erase operation. 0 = perform write only bit 3 wrerr: write error flag bit 1 = a write operation terminated prematurely (by device reset) 0 = write operation completed successfully bit 2 wren: write enable bit 1 = allows write cycle to flash data memory 0 = inhibits write cycle to flash data memory bit 1 wr: write control bit 1 = initiate a erase or write cycle 0 = write/erase cycle is complete bit 0 rd: read control bit 1 = initiate a read of flash data memory 0 = do not read flash data memory PIC16F570 ds40001684b-page 32 preliminary ? 2013 microchip technology inc. 6.0 i/o port as with any other register, the i/o register(s) can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at high- impedance) since the i/o control registers are all set. 6.1 porta porta is an 8-bit i/o register. the configuration word can set several i/os to alternate functions. when acting as alternate functions, the pins will read as ? 0 ? during a port read. 6.2 portb portb is an 8-bit i/o register. the portb pins can be configured with weak pull-ups and also for wake-up on change. the wake-up on change and weak pull-up functions are not pin-selectable. 6.3 portc portc is an 8-bit i/o register. 6.4 tris register the output driver control register is loaded with the contents of the w register by executing the tris instruction. a ? 1 ? from a tris register bit puts the corresponding output driver in a high-impedance mode. a ? 0 ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the only exception is the t0cki pin, which may be controlled by the option register (see register 4-2 ). tris registers are ?write-only?. active bits in these registers are set (output drivers disabled) upon reset. ? 2013 microchip technology inc. preliminary ds40001684b-page 33 PIC16F570 6.5 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 6-1 . all port pins, except the mclr pin which is input-only, may be used for both input and output oper- ations. for input operations, these ports are non-latch- ing. any input must be present until read by an input instruction (e.g., movf portb, w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the correspond- ing direction control bit in tris must be cleared (= 0 ). for use as an input, the corresponding tris bit must be set. any i/o pin (except mclr ) can be programmed individually as input or output. figure 6-1: block diagram of i/o pin (example shown of rb7 with weak pull-up and wake-up on change) data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: pin enabled as analog for cv ref or comparator. d ck q pin change rxpu cv ref 2 pin ebl comp pin ebl cv ref 2 comp i/o pin (1) (2) (2) PIC16F570 ds40001684b-page 34 preliminary ? 2013 microchip technology inc. 6.6 register definitions ? port control register 6-1: porta: porta register register 6-2: portb: portb register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ra<7:0> : porta i/o pin bits 1 = port pin is >v ih min. 0 = port pin is PIC16F570 ds40001684b-page 36 preliminary ? 2013 microchip technology inc. 6.7 i/o programming considerations 6.7.1 bidirectional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and rewrite the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit 5 of portb will cause all eight bits of portb to be read into the cpu, bit 5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bidirec- tional i/o pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. example 6-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired or?, ?wired and?). the resulting high output currents may damage the chip. example 6-1: read/modify/write instructions on an i/o port (e.g., PIC16F570) 6.7.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle ( figure 6-2 ). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 6-2: successive i/o operation ;initial portb settings ;portb<5:3> inputs ;portb<2:0> outputs ; ; portb latch portb pins ; -------------------- bcf portb, 5 ;--01 -ppp--11 pppp bcf portb, 4 ;--10 -ppp--11 pppp movlw 007h ; tris portb ;--10 -ppp--11 pppp ; note 1: the user may have expected the pin values to be ? --00 pppp ?. the 2nd bcf caused rb5 to be latched as the pin value (high). pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<5:0> movwf portb nop port pin sampled here nop movf portb , w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy ? t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) port pin written here ? 2013 microchip technology inc. preliminary ds40001684b-page 37 PIC16F570 notes: PIC16F570 ds40001684b-page 38 preliminary ? 2013 microchip technology inc. 7.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select: - edge select for external clock figure 7-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit of the option register. in timer mode, the timer0 module will increment every instruction cycle (without pres- caler). if tmr0 register is written, the increment is inhibited for the following two cycles ( figure 7-2 and figure 7-3 ). the user can work around this by writing an adjusted value to the tmr0 register. there are two types of counter mode. the first counter mode uses the t0cki pin to increment timer0. it is selected by setting the t0cs bit of the option regis- ter, setting the c1t0cs bit of the cm1con0 register and setting the c1outen bit of the cm1con0 regis- ter. in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit of the option register determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 7.1 ?using timer0 with an external clock? . the second counter mode uses the output of the comparator to increment timer0. it can be entered in by setting the t0cs bit of the option register, and clearing the c1t0cs bit of the cm1con0 register (c1outen [cm1con0<6>] does not affect this mode of operation). this enables an internal connection between the comparator and the timer0. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit, psa of the option register. clearing the psa bit will assign the prescaler to timer0. the pres- caler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 7.2 ?prescaler? details the operation of the prescaler. a summary of registers associated with the timer0 module is found in ta bl e 7 - 1 . figure 7-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register (see register 4-2 ). 2: the prescaler is shared with the watchdog timer. 3: the c1t0cs bit is in the cm1con0 register. t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg ps out (2-cycle delay) ps out data bus 8 psa (1) ps2 (1) , ps1 (1) , ps0 (1) 3 sync 0 1 comparator output c1t0cs (3) ? 2013 microchip technology inc. preliminary ds40001684b-page 39 PIC16F570 figure 7-2: timer0 timing: in ternal clock/no prescale figure 7-3: timer0 timing: internal clock/prescale 1:2 table 7-1: registers associated with timer0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page tmr0 timer0 module register ? cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 71 cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 72 option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 22 tris (1) i/o control registers (trisa, trisb, trisc) ? legend: shaded cells are not used by timer0. ? = unimplemented, x = unknown, u = unchanged. note 1: the tris of the t0cki pin is overridden when t0cs = 1 . pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 t0 + 2 nt0 nt0 + 1 nt0 + 2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter) pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 nt0 nt0 + 1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter) PIC16F570 ds40001684b-page 40 preliminary ? 2013 microchip technology inc. 7.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 7.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks ( figure 7-4 ). therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 2 tt0h) and low for at least 2 t osc (and a small rc delay of 2 tt0h). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling require- ment, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4 t osc (and a small rc delay of 4 tt0h) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of tt0h. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 7-4 shows the delay from the external clock edge to the timer incrementing. figure 7-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3 t osc to 7 t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4 t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. ? 2013 microchip technology inc. preliminary ds40001684b-page 41 PIC16F570 7.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (see section 8.7 ?watchdog timer (wdt)? ). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps<2:0> bits of the option register determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ? 0 ?s. 7.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during program execution). to avoid an unintended device reset, the following instruction sequence ( example 7-1 ) must be executed when changing the prescaler assignment from timer0 to the wdt. example 7-1: changing prescaler (timer0 ?? wdt) to change the prescaler from the wdt to the timer0 module, use the sequence shown in example 7-2 . this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 7-2: changing prescaler (wdt ?? timer0) note: the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt and vice versa. clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw b'00xx1111' clrwdt ;ps<2:0> are 000 or 001 movlw b'00xx1xxx' ;set postscaler to option ;desired wdt rate clrwdt ;clear wdt and ;prescaler movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option PIC16F570 ds40001684b-page 42 preliminary ? 2013 microchip technology inc. figure 7-5: block diagram of the timer0/wdt prescaler t cy (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m mux watchdog timer psa (1) 0 1 0 1 wdt time-out ps<2:0> (1) 8 psa (1) wdt enable bit 0 1 0 1 data bus 8 psa (1) t0cs (1) m u x m u x u x t0se (1) note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register (see register 4-2 ). t0cki pin 0 1 c1tocs comparator output ? 2013 microchip technology inc. preliminary ds40001684b-page 43 PIC16F570 notes: PIC16F570 ds40001684b-page 44 preliminary ? 2013 microchip technology inc. 8.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. the PIC16F570 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power- saving operating modes and offer code protection. these features are: ? oscillator selection ?reset: - power-on reset (por) - brown-out reset (bor) - device reset timer (drt) - wake-up from sleep on pin change ? interrupts ? automatic context saving ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? ?clock out the device has a watchdog timer, which can be shut off only through configuration bit wdte. the watchdog timer runs off of its own rc oscillator for added reliability. there is also a device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. the drt can be enabled with the drten configuration bit. for the hs, xt or lp oscillator options, the 18 ms (nominal) delay is always provided by the device reset timer and the drten bit is ignored. when using the ec clock, intrc or extrc oscillator options, there is a standard delay of 10 us on power-up, which can be extended to 18 ms with the use of the drt timer. with the drt timer on-chip, most applications require no additional external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pin or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4/8 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 8.1 configuration bits the PIC16F570 configuration words consist of 12 bits, although some bits may be unimplemented and read as ? 1 ?. configuration bits can be programmed to select various device configurations (see register 8-1 ). ? 2013 microchip technology inc. preliminary ds40001684b-page 45 PIC16F570 8.2 register definitions ? configuration word register 8-1: config: co nfiguration word register u-1 u-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? drten boren cpsw ioscfs ?cp wdte fosc2 fosc1 fosc0 bit 11 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 11-10 unimplemented: read as ? 1 ? bit 9 drten: device reset timer enable bit 1 =drt enabled (18ms) 0 =drt disabled bit 8 boren: brown-out reset enable bit 1 = bor enabled 0 = bor disabled bit 7 cpsw : code protection bit ? self-writable memory 1 = code protection off 0 = code protection on bit 6 ioscfs: internal oscillator frequency select bit 1 = 8 mhz intosc speed 0 = 4 mhz intosc speed bit 5 unimplemented: read as ? 1 ? bit 4 cp : code protection bit ? user program memory 1 = code protection off 0 = code protection on bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 000 = lp oscillator and automatic 18 ms drt (drten fuse ignored) 001 = xt oscillator and automatic 18 ms drt (drten fuse ignored) 010 = hs oscillator and automatic 18 ms drt (drten fuse ignored) 011 = ec oscillator with i/o function on osc2/clkout and 10 us start-up time (2,3) 100 = intrc with i/o function on osc2/clkout and 10 us start-up time (2,3) 101 = intrc with clkout function on osc2/clkout and 10 us start-up time (2,3) 110 = extrc with i/o function on osc2/clkout and 10 us start-up time (2,3) 111 = extrc with clkout function on osc2/clkout and 10 us start-up time (2,3) note 1: refer to the ? PIC16F570 memory programming specification ? (ds41670), to determine how to access the configuration word. 2: drt length and start-up time are functions of the clock mode selection. it is the responsibility of the application designer to ensure the use of either will result in acceptable operation. refer to section 15.0 ?electrical characteristics? for v dd rise time and stability requirements for this mode of operation. 3: the optional drten fuse can be used to extend the start-up time to 18 ms. PIC16F570 ds40001684b-page 46 preliminary ? 2013 microchip technology inc. 8.3 oscillator configurations 8.3.1 oscillator types the PIC16F570 device can be operated in up to six different oscillator modes. the user can program up to three configuration bits (fosc<2:0>). to select one of these modes: ? lp: low-power crystal ? xt: crystal/resonator ? hs: high-speed crystal/resonator ? intrc: internal 4/8 mhz oscillator ? extrc: external resistor/capacitor ? ec: external high-speed clock input 8.3.2 crystal oscillator/ceramic resonators in hs, xt or lp modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation ( figure 8-1 ). the PIC16F570 oscillator designs require the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs, xt or lp modes, the device can have an external clock source drive the osc1/clkin pin ( figure 8-2 ). in this mode, the output drive levels on the osc2 pin are very weak. if the part is used in this fashion, then this pin should be left open and unloaded. also when using this mode, the external clock should observe the frequency limits for the clock mode chosen (hs, xt or lp). figure 8-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 8-2: external clock input operation (hs, xt, lp or ec osc configuration) table 8-1: capacitor selection for ceramic resonators note 1: this device has been designed to per- form to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance charac- teristics than its earlier version. these differences may cause this device to perform differently in your application than the earlier version of this device. 2: the user should verify that the device oscillator starts and performs as expected. adjusting the loading capaci- tor values and/or the oscillator mode may be required. osc. type resonator freq. cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf hs 16 mhz 10-47 pf 10-47 pf note 1: these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approx. value = 10 m ? . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic ? device clock from ext. system pic ? device osc2/clkout osc1/clkin osc2/clkout (1) ec, hs, xt, lp note 1: available in ec mode only. ? 2013 microchip technology inc. preliminary ds40001684b-page 47 PIC16F570 table 8-2: capacitor selection for crystal oscillator (2) 8.3.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 8-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 8-3: external parallel resonant crystal oscillator circuit figure 8-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 ? resistors provide the negative feedback to bias the inverters in their linear region. figure 8-4: external series resonant crystal oscillator circuit 8.3.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 8-5 shows how the r/c combination is con- nected to the PIC16F570 device. for r ext values below 3.0 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 5.0 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no external capacitance or with values below 20 pf, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. osc. type resonator freq. cap. range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs 20 mhz 15-47 pf 15-47 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. 2: these values are for design guidance only. rs may be required to avoid over- driving crystals with low drive level specifi- cation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to o t h e r devices pic ? device 330 74as04 74as04 pic ? device clkin to other devices xtal 330 74as04 0.1 mf PIC16F570 ds40001684b-page 48 preliminary ? 2013 microchip technology inc. figure 8-5: external rc oscillator mode 8.3.5 internal 4/8 mhz rc oscillator the internal rc oscillator provides a fixed 4/8 mhz (nominal) system clock at v dd = 5v and 25c, (see section 15.0 ?electrical characteristics? for information on variation over voltage and temperature). in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal rc oscillator. this location is always non-code protected, regardless of the code- protect settings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register or ignoring it. osccal, when written to with the calibration value, will ?trim? the internal oscillator to remove process variation from the oscillator frequency. for the PIC16F570 device, only bits <7:1> of osccal are used for calibration. see register 4-3 for more information. note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. note: the bit 0 of the osccal register is unimplemented and should be written as ? 0 ? when modifying osccal for compatibility with future devices. v dd r ext c ext v ss osc1 internal clock n f osc /4 osc2/clkout pic ? device ? 2013 microchip technology inc. preliminary ds40001684b-page 49 PIC16F570 8.4 reset the device differentiates between various kinds of reset: ? power-on reset (por) ? brown-out reset (bor) ?mclr reset during normal operation ?mclr reset during sleep ? wdt time-out reset during normal operation ? wdt time-out reset during sleep ? wake-up from sleep on pin change some registers are not reset in any way, they are unknown on por/bor and unchanged in any other reset. most other registers are reset to ?reset state? on power-on reset (por)/brown-out reset (bor), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal oper- ation. the exceptions to this are the t o and p d bits. they are set or cleared differently in different reset sit- uations. these bits are used in software to determine the nature of reset. see ta bl e 4 - 1 for a full description of reset states of all registers. table 8-3: reset condition for special registers status addr: 03h power-on reset (por) or brown-out reset (bor) 0001 1xxx mclr reset during normal operation 000u uuuu mclr reset during sleep 0001 0uuu wdt reset during sleep 0000 0uuu wdt reset normal operation 0000 uuuu wake-up from sleep on pin change 1001 0uuu wake-up from sleep on comparator change 0101 0uuu legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?. PIC16F570 ds40001684b-page 50 preliminary ? 2013 microchip technology inc. 8.4.1 mclr enable this master clear (mclr ) feature and its associated pull-up are always enabled on this device. the pin is assigned to be an input-only pin function. figure 8-6: mclr input pin 8.5 power-on reset (por) the PIC16F570 device incorporates an on-chip power- on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the internal por, an inter- nal weak pull-up resistor is implemented using a transistor (refer to tab l e 1 5- 11 for the pull-up resistor ranges). this will eliminate external rc components usually needed to create a power-on reset. a maxi- mum rise time for v dd is specified. see section 15.0 ?electrical characteristics? for details. when the device starts normal operation (exit the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 8-7 . the power-on reset circuit and the device reset timer (see section 8.6 ?device reset timer (drt)? ) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is held low is shown in figure 8-8 . v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 8-9 , the on-chip power-on reset feature is being used (mclr is tied to v dd or pulled high by its internal pull-up). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 8-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we rec- ommend that external rc circuits be used to achieve longer por delay times ( figure 8-9 ). for additional information, refer to application notes an522, ?power-up considerations? (ds00522) and an607, ?power-up trouble shooting? (ds00607). mclr /v pp internal mclr note: when the device starts normal operation (exit the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. ? 2013 microchip technology inc. preliminary ds40001684b-page 51 PIC16F570 figure 8-7: simplified block di agram of on-chip reset circuit figure 8-8: time-out sequ ence on power-up (mclr pulled low) figure 8-9: time-out sequ ence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd m clr /v pp power-up detect por (power-on reset) wdt reset chip reset wake-up on pin change reset start-up timer (10 us wdt time-out pin change sleep mclr reset or 18 ms) comparator change wake-up on comparator change v dd mclr internal por drt time-out internal reset tdrt v dd mclr internal por drt time-out internal reset tdrt PIC16F570 ds40001684b-page 52 preliminary ? 2013 microchip technology inc. figure 8-10: time-out sequ ence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset tdrt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 ? v dd min. ? 2013 microchip technology inc. preliminary ds40001684b-page 53 PIC16F570 8.6 device reset timer (drt) on the PIC16F570 device, the drt runs any time the device is powered up. drt runs from reset and varies based on oscillator selection and reset type (see table 8-4 ). the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min. and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition after mclr has reached a logic high (v ih mclr ) level. using an external rc network con- nected to the mclr input is not required in most cases. this allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of that pin as a general purpose input. the device reset time delays will vary from chip-to- chip due to v dd , temperature and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out from sleep. this is particularly important for applications using the wdt to wake from sleep mode automatically. reset sources are por, mclr , wdt time-out and wake-up on pin or comparator change. see section 8.10.2 ?wake-up from sleep? , notes 1, 2 and 3 . 8.7 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator, which does not require any external components. this rc oscillator is separate from the external rc oscillator of the osc1/clkin pin and the internal 4/8 mhz oscillator. this means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset, generates a device reset. the to bit of the status register will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the configuration wdte as a ? 0 ? (see section 8.1 ?configuration bits? ). refer to the PIC16F570 programming specifications to determine how to access the configuration word. table 8-4: typical drt periods 8.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst-case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 8.7.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. oscillator configuration por reset subsequent resets hs, xt, lp 18 ms 18 ms ec 10 us 10 ? s intosc, extrc 10 us 10 ? s PIC16F570 ds40001684b-page 54 preliminary ? 2013 microchip technology inc. figure 8-11: watchdo g timer block diagram table 8-5: registers associated with the watchdog timer 8.8 time-out sequence (to ) and power-down (pd ) reset status the to and p d bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. table 8-6: to /pd status after reset name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page option r bw u r bp u t0cs t0se psa ps2 ps1 ps0 22 legend: shaded boxes = not used by watchdog timer. ( figure 7-1 ) postscaler note 1: psa, ps<2:0> are bits in the option register (see register 4-2 ). wdt time-out watchdog time from timer0 clock source wdt enable configuration bit psa postscaler 8-to-1 mux ps<2:0> (1) ( figure 7-4 ) to timer0 0 1 m u x 1 0 psa (1) mux to pd reset caused by 00 wdt wake-up from sleep 0u wdt time-out (not from sleep) 10 mclr wake-up from sleep 11 power-up or brown-out reset uu mclr not during sleep legend: u = unchanged note 1: the to and pd bits maintain their status ( u ) until a reset occurs. a low pulse on the mclr input does not change the to and pd status bits. ? 2013 microchip technology inc. preliminary ds40001684b-page 55 PIC16F570 8.9 brown-out reset (bor) a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. the brown-out reset feature is enabled by the boren configuration bit. if v dd falls below v bor for greater than parameter (t bor ) (see figure 8-12 ), the brown-out situation will reset the device. this will occur regardless of v dd slew rate. a reset is not insured to occur if v dd falls below v bor for less than parameter (t bor ). please see section 15.0 ?electrical characteristics? for the v bor specification and other parameters shown in figure 8-12 . on any reset (power-on, brown-out reset, watchdog timer, etc.), the chip will remain in reset until v dd rises above v bor (see figure 8-12 ). if enabled, the device reset timer will now be invoked, and will keep the chip in reset an additional 18 ms. if v dd drops below v bor while the device reset timer is running, the chip will go back into a brown-out reset and the device reset timer will be re-initialized. once v dd rises above v bor , the device reset timer will execute a 18 ms reset. figure 8-12: brown-out rese t timing and characteristics figure 8-13: brown -out situations note: the device reset timer is enabled by the drten bit in the configuration word register. v bor v dd (device in brown-out reset) (device not in brown-out reset) t drt t bor reset (due to bor) v bor + v hyst 18 ms v bor v dd internal reset v bor v dd internal reset 18 ms < 18 ms 18 ms v bor v dd internal reset (drten = 1 ) (drten = 1 ) (drten = 1 ) PIC16F570 ds40001684b-page 56 preliminary ? 2013 microchip technology inc. 8.10 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 8.10.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit of the status register is set, the pd bit of the status register is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was exe- cuted (driving high, driving low or high-impedance). for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the m clr /v pp pin must be at a logic high level if mclr is enabled. 8.10.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on m clr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). 3. from an interrupt source, see section 8.11 ?interrupts? for more information. on waking from sleep, the processor will continue to execute the instruction immediately following the sleep instruction. if the wur bit is also set, upon waking from sleep, the device will reset. if the gie bit is also set, upon waking from sleep, the processor will branch to the interrupt vector. please see section 8.11 ?interrupts? for more information. the to and pd bits can be used to determine the cause of the device reset. the to bit is cleared if a wdt time-out occurred and subsequently caused a wake-up. the pd bit, which is set on power-up, is cleared when sleep is invoked. . the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. 8.11 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. these following interrupt sources are available on the PIC16F570 device: ? timer0 overflow ? adc completion ? comparator output change ? interrupt-on-change pin refer to the corresponding chapters for details. 8.11.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon0 register ? interrupt enable bit(s) for the specific interrupt event(s) the enable bits for specific interrupts can be found in the intcon1 register. an interrupt is recorded for a specific interrupt via flag bits found in the intcon0 register. the adc conversion flag and the timer0 overflow flags will be set regardless of the status of the gie and individual interrupt enable bits. the comparator and interrupt-on-change flags must be enabled for use. one or both of the comparator outputs can be enabled to affect the interrupt flag by setting the c 1wu bit in the cm1con0 register and the c 2wu bit in the cm2con0 register. the interrupt-on- change flag is enabled by setting the r bw u bit in the option register. note: a reset generated by a wdt time-out does not drive the mclr pin low. caution: right before entering sleep, read the input pins. when in sleep, wake-up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately even if no pins change while in sleep mode. caution: right before entering sleep, read the comparator configuration register(s) cm1con0 and cm2con0. when in sleep, wake-up occurs when the com- parator output bit c1out and c2out change from the state they were in at the last reading. if a wake-up on comparator change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately, even if no pins change while in sleep mode. ? 2013 microchip technology inc. preliminary ds40001684b-page 57 PIC16F570 the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? several registers are automatically switched to a secondary set of registers to store critical data. (see section 8.12 ?automatic context switch- ing? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. 8.12 automatic context switching while the device is executing from the isr, a secondary set of w, status, fsr and bsr registers are used by the cpu. these registers are still addressed at the same location, but hold persistent, independent values for use inside the isr. this allows the contents of the primary set of registers to be unaffected by interrupts in the main line execution. the contents of the secondary set of context registers are visible in the sfr map as the iw, istatus, ifsr and ibsr registers. when executing code from within the isr, these registers will read back the main line context, and vice versa. the retfie instruction exits the isr by popping the previous address from the stack, switching back to the original set of critical registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 8.13 interrupts during sleep any of the interrupt sources can be used to wake from sleep. to wake from sleep, the peripheral must be operating without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to the section 8.10 ?power-down mode (sleep)? for more details. table 8-7: interrupt priorities note 1: individual interrupt flag bits may be set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again. 3: all interrupts should be disabled prior to executing writes or row erases in the self- writable flash data memory. vector or in sleep gie wur wake-up and vector wake-up reset wake-up inline watchdog wake-up inline watchdog wake-up reset 1 x x x x 1 1 1 1 1 1 0 0 0 0 PIC16F570 ds40001684b-page 58 preliminary ? 2013 microchip technology inc. 8.14 register definitions ? interrupt control register 8-2: intcon0 register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 adif cwif t0if rbif ? ? ? gie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adif: a/d converter interrupt flag bit 1 = a/d conversion complete (must be cleared by software) 0 = a/d conversion has not completed or has not been started bit 6 cwif: comparator 1 or 2 interrupt flag bit 1 = comparator interrupt-on-change has occurred (1) 0 = no change in comparator 1 or 2 output bit 5 t0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared by software) 0 = tmr0 register did not overflow bit 4 rbif: portb interrupt-on-change flag bit 1 = wake-up or interrupt has occurred (cleared in software) (2) 0 = wake-up or interrupt has not occurred bit 3-1 unimplemented: read as ? 0 ? bit 0 gie: global interrupt enable bit 1 = interrupt sets pc to address 0x004 (vector to isr) 0 = interrupt causes wake-up and inline code execution note 1: this bit only functions when the c1wu or c2wu bits are set (see register 10-1 and register 10-2 ). 2: the r bw u bit of the option register must be set to enable this function (see register 4-2 ). ? 2013 microchip technology inc. preliminary ds40001684b-page 59 PIC16F570 register 8-3: intcon1 register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 adie cwie t0ie rbie ? ? ? wur bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adie: a/d converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 6 cwie: comparator 1 and 2 interrupt enable bit 1 = enables the comparator 1 and 2 interrupt 0 = disables the comparator 1 and 2 interrupt bit 5 t0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 rbie: portb on pin change interrupt enable bit 1 = interrupt-on-change pin enabled 0 = interrupt-on-change pin disabled bit 3-1 unimplemented: read as ? 0 ? bit 0 wur: wake-up reset enable bit 1 = interrupt source causes device reset on wake-up 0 = interrupt source wakes up device from sleep (vector to isr or inline execution) PIC16F570 ds40001684b-page 60 preliminary ? 2013 microchip technology inc. 8.15 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (osccal) can be read, regardless of the code protection bit setting. 8.16 id locations four memory locations are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower four bits of the id locations and always program the upper eight bits as ? 0 ?s. 8.17 in-circuit serial programming? the PIC16F570 microcontroller can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the devices are placed into a program/verify mode by holding the icspclk and icspdat pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). icspclk becomes the programming clock and icspdat becomes the programming data. both icspclk and icspdat are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the PIC16F570 programming specifications. a typical in-circuit serial programming connection is shown in figure 8-14 . figure 8-14: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections v dd v ss mclr /v pp icspclk icspdat +5v 0v v pp clk data v dd pic ? device ? 2013 microchip technology inc. preliminary ds40001684b-page 61 PIC16F570 notes: PIC16F570 ds40001684b-page 62 preliminary ? 2013 microchip technology inc. 9.0 analog-to-digital (a/d) converter the a/d converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 clock divisors the adc has four clock source settings adcs<1:0>. there are three divisor values 16, 8 and 4. the fourth setting is intosc with a divisor of four. these settings will allow a proper conversion when using an external oscillator at speeds from 20 mhz to 350 khz. using an external oscillator at a frequency below 350 khz requires the adc oscillator setting to be intosc/4 (adcs<1:0> = 11 ) for valid adc results. the adc requires 13 t ad periods to complete a conversion. the divisor values do not affect the number of t ad periods required to perform a conversion. the divisor values determine the length of the t ad period. when the adcs<1:0> bits are changed while an adc conversion is in process, the new adc clock source will not be selected until the next conversion is started. this clock source selection will be lost when the device enters sleep. 9.1.1 voltage reference there is no external voltage reference for the adc. the adc reference voltage will always be v dd . 9.1.2 analog mode selection the ans<7:0> bits are used to configure pins for analog input. upon any reset, ans<7:0> defaults to ff. this configures the affected pins as analog inputs. pins configured as analog inputs are not available for digital output. users should not change the ans bits while a conversion is in process. ans bits are active regardless of the condition of adon. 9.1.3 adc channel selection the chs bits are used to select the analog channel to be sampled by the adc. the chs<3:0> bits can be changed at any time without adversely effecting a con- version. to acquire an external analog signal, the chs<3:0> selection must match one of the pin(s) selected by the ans<7:0> bits. when the adc is on (adon = 1 ) and a channel is selected that is also being used by the comparator, then both the comparator and the adc will see the analog voltage on the pin. when the chs<3:0> bits are changed during an adc conversion, the new channel will not be selected until the current conversion is completed. this allows the current conversion to complete with valid results. all channel selection information will be lost when the device enters sleep. 9.1.4 the go/done bit the go/done bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. setting the go/done bit starts a conversion. when the conversion is complete, the adc module clears the go/done bit and sets the adif bit in the intcon0 register. a conversion can be terminated by manually clearing the go/done bit while a conversion is in process. manual termination of a conversion may result in a partially converted result in adres. the go/done bit is cleared when the device enters sleep, stopping the current conversion. the adc does not have a dedicated oscillator, it runs off of the instruction clock. therefore, no conversion can occur in sleep. the go/done bit cannot be set when adon is clear. 9.1.5 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 9-1 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 9-1 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 9-1 may be used. this equation assumes that 1/2 lsb error is used (256 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. note: the adc clock is derived from the instruction clock. the adcs divisors are then applied to create the adc clock note: it is the user?s responsibility to ensure that the use of the adc and op amp simultaneously on the same pin does not adversely affect the signal being monitored or adversely effect device operation. ? 2013 microchip technology inc. preliminary ds40001684b-page 63 PIC16F570 equation 9-1: acquisition time example figure 9-1: analog input module note 1: the charge holding capacitor (c hold ) is not discharged after each conversion. 2: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. assumptions: temperature = 50c and external impedance of 10 k ? 5.0v v dd tacq = amplifier settling time + hold capacitor charging time + temperature coefficient =t amp + t c + t coff =2 ? s + t c + [(temperature - 25c)(0.05 ? s/c)] solving for tc: tc = c hold (r ic + r ss + r s ) in(1/512) = -25pf (l k ? + 7 k ? + 10 k ? ) in(0.00196) =2.81 ? s therefore: tacq = 2 ? s + 2.81 ? s + [(50c-25c)(0.0 5 ? s/c)] =6.06 ? s c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic ? 1k sampling switch ss rss c hold = 25 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd 500 na r ss legend: cpin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance ss = sampling switch c hold = sample/hold capacitance PIC16F570 ds40001684b-page 64 preliminary ? 2013 microchip technology inc. 9.1.6 analog conversion result register the adres register contains the results of the last conversion. these results are present during the sampling period of the next analog conversion process. after the sampling period is over, adres is cleared (= 0 ). a ?leading one? is then right shifted into the adres to serve as an internal conversion complete bit. as each bit weight, starting with the msb, is converted, the leading one is shifted right and the converted bit is stuffed into adres. after a total of nine right shifts of the ?leading one? have taken place, the conversion is complete; the ?leading one? has been shifted out and the go/done bit is cleared. if the go/done bit is cleared in software during a conversion, the conversion stops and the adif bit will not be set to a ? 1 ?. the data in adres is the partial conversion result. this data is valid for the bit weights that have been converted. the position of the ?leading one? determines the number of bits that have been converted. the bits that were not converted before the go/done was cleared are unrecoverable. register 9-1: adcon0: a/d control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 adcs1 adcs0 chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 adcs<1:0>: adc conversion clock select bits 00 =f osc /16 01 =f osc /8 10 =f osc /4 11 = intosc/4 bit 5-2 chs<3:0>: adc channel select bits (1) 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1xxx = reserved 1111 = 0.6v fixed input reference (v fir ) bit 1 go/done : adc conversion status bit (2) 1 = adc conversion in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc is done converting. 0 = adc conversion completed/not in progress. manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 adon: adc enable bit 1 = adc module is operating 0 = adc module is shut-off and consumes no power note 1: chs<3:0> bits default to 1 after any reset. 2: if the adon bit is clear, the go/done bit cannot be set. ? 2013 microchip technology inc. preliminary ds40001684b-page 65 PIC16F570 example 9-1: performing an analog-to-digital conversion example 9-2: channel selection change during conversion register 9-2: adres: a/d conversion results register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0> : adc result register bits ;sample code operates out of bank0 movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 2 ;setup for read of ;channel 1 bsf adcon0, 1 ;start conversion loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion bsf adcon0, 2 ;setup for read of ;channel 1 loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 1 ;start conversion bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result clrf adcon0 ;optional: returns ;pins to digital mode and turns off ;the adc module PIC16F570 ds40001684b-page 66 preliminary ? 2013 microchip technology inc. 9.1.7 sleep this adc does not have a dedicated adc clock, and therefore, no conversion in sleep is possible. if a conversion is underway and a sleep command is executed, the go/done and adon bit will be cleared. this will stop any conversion in process and power- down the adc module to conserve power. due to the nature of the conversion process, the adres may con- tain a partial conversion. at least one bit must have been converted prior to sleep to have partial conver- sion data in adres. the adcs and chs bits are reset to their default condition; ans<7:0> = 1s and chs<3:0> = 1s . ? for accurate conversions, t ad must meet the following: ?500ns < t ad < 50 ? s ?t ad = 1 /(f osc /divisor) shaded areas indicate t ad out of range for accurate conversions. if analog input is desired at these frequencies, use intosc/8 for the adc clock source. table 9-1: t ad for adcs settings with various oscillators table 9-2: effects of sleep on adcon0 source adcs <1:0> divisor 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz 500 khz 350 khz 200 khz 100 khz 32 khz intosc 11 4 ? ?.5 ? s1 ? s ? ? ? ? ? ? fosc 10 4 .2 ? s .25 ? s.5 ? s1 ? s4 ? s8 ? s11 ? s20 ? s40 ? s 125 ? s fosc 01 8 .4 ? s.5 ? s1 ? s2 ? s8 ? s16 ? s23 ? s40 ? s 80 ? s 250 ? s fosc 00 16 .8 ? s1 ? s2 ? s4 ? s16 ? s32 ? s46 ? s 80 ? s 160 ? s 500 ? s ans<7:0> adcs1 adcs0 chs<3:0> go/done adon entering sleep unchanged 11 1 0 0 wake or reset 111100 ? 2013 microchip technology inc. preliminary ds40001684b-page 67 PIC16F570 notes: PIC16F570 ds40001684b-page 68 preliminary ? 2013 microchip technology inc. 10.0 comparator(s) this device contains two comparators and a comparator voltage reference. figure 10-1: compar ators block diagram + - c1in+ c1in- fixed input c1on c1pol c1t0cs c1 out c1outen c1out (r egister) t0cki pin t0cki qd s read cm1con0 c2wu c1pref c1nref + - c2in+ c2in- c2on c2pol c2pref1 c2nref cv ref c2pref2 c2 out c2outen c2out (r egister) qd s cw if read cm2con0 c1wu 1 0 1 0 1 0 1 0 1 0 1 0 reference (v fir ) ? 2013 microchip technology inc. preliminary ds40001684b-page 69 PIC16F570 10.1 comparator operation a single comparator is shown in figure 10-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. the shaded area of the output of the comparator in figure 10-2 represent the uncertainty due to input offsets and response time. see table 15-2 for common mode voltage. figure 10-2: single comparator 10.2 comparator reference an internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly ( figure 10-2 ). please see section 11.0 ?comparator voltage reference module? for internal reference specifications. 10.3 comparator response time response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level. if the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. please see table 15-2 for comparator response time specifications. 10.4 comparator output the comparator output is read through the cxout bit in the cm1con0 or cm2con0 register. this bit is read-only. the comparator output may also be used externally, see section 10.1 ?comparator opera- tion? . 10.5 comparator wake-up flag the comparator wake-up flag bit, cwif, in the intcon0 register, is set whenever all of the following conditions are met: ?c1wu = 0 (cm1con0<0>) or c2wu = 0 (cm2con0<0>) ? cm1con0 or cm2con0 has been read to latch the last known state of the c1out and c2out bit ( movf cm1con0 , w ) ? the output of a comparator has changed state the wake-up flag may be cleared in software or by another device reset. 10.6 comparator operation during sleep when the comparator is enabled it is active. to minimize power consumption while in sleep mode, turn off the comparator before entering sleep. 10.7 effects of reset a power-on reset (por) forces the cmxcon0 register to its reset state. this forces the comparator input pins to analog reset mode. device current is minimized when analog inputs are present at reset time. 10.8 analog input connection considerations a simplified circuit for an analog input is shown in figure 10-3 . since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. ? + v in + v in - result result v in - v in + note: analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. PIC16F570 ds40001684b-page 70 preliminary ? 2013 microchip technology inc. figure 10-3: analog input mode va r s < 10 k a in c pin 5pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin r ic = interconnect resistance r s = source impedance va = analog voltage ? 2013 microchip technology inc. preliminary ds40001684b-page 71 PIC16F570 10.9 register definitions ? comparator control register 10-1: cm1con0: comparator c1 control register r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c1outen : comparator output enable bit (1) 1 = output of comparator is not placed on the c1out pin 0 = output of comparator is placed in the c1out pin bit 5 c1pol: comparator output polarity bit 1 = output of comparator is not inverted 0 = output of comparator is inverted bit 4 c1t0cs : comparator tmr0 clock source bit 1 = tmr0 clock source selected by t0cs control bit 0 = comparator output used as tmr0 clock source bit 3 c1on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c1nref: comparator negative reference select bit (2) 1 = c1in- pin 0 = 0.6v fixed input reference (v fir ) bit 1 c1pref: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c1in- pin bit 0 c1wu : comparator wake-up on change enable bit (3) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled note 1: overrides tris control of ra2. 2: when this bit selects an i/o pin and the comparator is turned on, this feature will override the tris and ansel settings to make the respective pin an analog input. the value in the ansel register, however, is not over-written. when the comparator is turned off, the respective pin will revert back to the original tris and ansel settings. 3: the c1wu bit must be set to enable the cwif function. see the intcon0 register ( register 8-2 ) for more information. PIC16F570 ds40001684b-page 72 preliminary ? 2013 microchip technology inc. register 10-2: cm2con0: comparator c2 control register table 10-1: registers associated with comparator module r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c2outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c2out pin 0 = output of comparator is placed in the c2out pin bit 5 c2pol: comparator output polarity bit (2) 1 = output of comparator not inverted 0 = output of comparator inverted bit 4 c2pref2: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c2in- pin bit 3 c2on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c2nref: comparator negative reference select bit (2) 1 = c2in- pin 0 = cv ref bit 1 c2pref1: comparator positive reference select bit (2) 1 = c2in+ pin 0 = c2pref2 controls analog input selection bit 0 c2wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled. note 1: overrides tris control of rc4. 2: when comparator is turned on, these control bits assert themselves. otherwise, the other registers have precedence. 3: the c2wu bit must be set to enable the cwif function. see the intcon0 register ( register 8-2 ) for more information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page status pa2 pa1 pa0 to pd zdcc 21 cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 71 cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 72 tris i/o control register (trisa, trisb, trisc) ? legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?, q = depends on condition. ? 2013 microchip technology inc. preliminary ds40001684b-page 73 PIC16F570 notes: PIC16F570 ds40001684b-page 74 preliminary ? 2013 microchip technology inc. 11.0 comparator voltage reference module the comparator voltage reference module also allows the selection of an internally generated voltage reference for one of the c2 comparator inputs. the vrcon register ( register 11-1 ) controls the voltage reference module shown in figure 11-1 . 11.1 configuring the voltage reference the voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. equation 11-1 determines the output voltages: equation 11-1: 11.2 voltage reference accuracy the full range of v ss to v dd cannot be realized due to construction of the module. the transistors on the top and bottom of the resistor ladder network ( figure 11-1 ) keep cv ref from approaching v ss or v dd . the exception is when the module is disabled by clearing the vren bit of the vrcon register. when disabled, the reference voltage is v ss when vr<3:0> is ? 0000 ? and the vrr bit of the vrcon register is set. this allows the comparator to detect a zero-crossing and not consume the cv ref module current. the voltage reference is v dd derived and, therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in section 15.0 ?electrical characteristics? . vrr = 1 (low range): vrr = 0 (high range): cv ref = (v dd /4) + (vr<3:0> x v dd /32) cv ref = (vr<3:0>/24) x v dd register 11-1: vrcon: voltage reference control register r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 vren vroe1 vroe2 vrr vr3 vr2 vr1 vr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 vren: cv ref enable bit 1 = cv ref is powered on 0 = cv ref is powered down, no current is drawn bit 6 vroe1: cv ref 1 output enable bit (1) 1 = cv ref 1 output is enabled 0 = cv ref 1 output is disabled bit 5 vroe2: cv ref 2 output enable bit (1) 1 = cv ref 2 output is enabled 0 = cv ref 2 output is disabled bit 4 vrr: cv ref range selection bit 1 = low range 0 = high range bit 3-0 vr<3:0> cv ref value selection bits when v rr = 1 : cv ref = (vr<3:0>/24)*v dd when v rr = 0 : cv ref = v dd /4+(vr<3:0>/32)*v dd note 1: when this bit is set, the tris for the cv ref x pin is overridden and the analog voltage is placed on the cv ref x pin. ? 2013 microchip technology inc. preliminary ds40001684b-page 75 PIC16F570 figure 11-1: comparator voltage reference block diagram table 11-1: registers associated with comparator voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page vrcon vren vroe1 vroe2 vrr vr3 vr2 vr1 vr0 74 cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 72 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?, q = value depends on condition. v dd 8r r r vren 16-1 analog mux cv ref to comparator 2 input vr<3:0> v ren vr<3:0> = 0000 vrr vrr 8r rr 16 stages cv ref x v roe PIC16F570 ds40001684b-page 76 preliminary ? 2013 microchip technology inc. 12.0 operational amplifier (opa) module the opa module has the following features: ? two independent operational amplifiers ? external connections to all ports ? 3 mhz gain bandwidth product (gbwp) 12.1 opacon register the opa module is enabled by setting the opaxon bit of the opacon register. figure 12-1: opa module block diagram note: when opa1 or opa2 is enabled, the op1 pin or op2 pin, respectively, is driven by the op amp output, not by the port driver. refer to table 15-13 for the electrical specifications for the op amp output drive capability. opa1 opacon ? 2013 microchip technology inc. preliminary ds40001684b-page 77 PIC16F570 register 12-1: opacon: op am p control register 12.2 effects of a reset a device reset forces all registers to their reset state. this disables both op amps. 12.3 opa module performance common ac and dc performance specifications for the opa module: ? common mode voltage range ? leakage current ? input offset voltage ? open loop gain ? gain bandwidth product (gbwp) common mode voltage range is the specified voltage range for the op+ and op- inputs, for which the opa module will perform to within its specifications. the opa module is designed to operate with input voltages between 0 and v dd -1.4v. behavior for common mode voltages greater than v dd -1.4v, or below 0v, are beyond the normal operating range. leakage current is a measure of the small source or sink currents on the op+ and op- inputs. to minimize the effect of leakage currents, the effective impedances connected to the op+ and op- inputs should be kept as small as possible and equal. input offset voltage is a measure of the voltage differ- ence between the op+ and op- inputs in a closed loop circuit with the opa in its linear region. the offset volt- age will appear as a dc offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. the input offset voltage is also affected by the common mode voltage. open loop gain is the ratio of the output voltage to the differential input voltage, (op+) - (op-). the gain is greatest at dc and falls off with frequency. gain bandwidth product or gbwp is the frequency at which the open loop gain falls off to 0 db. 12.4 effects of sleep when enabled, the op amps continue to operate and consume current while the processor is in sleep mode. table 12-1: registers associated with the opa module u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? opa2on opa1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 opa2on: op amp enable bit 1 = op amp 2 is enabled 0 = op amp 2 is disabled bit 0 opa1on: op amp enable bit 1 = op amp 1 is enabled 0 = op amp 1 is disabled name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansel ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 35 opacon ? ? ? ? ? ?opa2onopa1on 77 tris i/o control registers (trisa, trisb, trisc) ? legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for the opa module. PIC16F570 ds40001684b-page 78 preliminary ? 2013 microchip technology inc. 13.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories. ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 12-bit word divided into an opcode , which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the formats for each of the categories is presented in figure 13-1 , while the various opcode fields are summarized in table 13-1 . for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the number of the bit affected by the operation, while ?f? represents the number of the file in which the bit is located. for literal and control operations, ?k? represents an 8 or 9-bit constant or literal value. table 13-1: opcode field descriptions all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. figure 13-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ?h? signifies a hexadecimal digit. figure 13-1: general format for instructions field description f register file address (0x00 to 0x1f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ?f?) default is d = 1 label label name tos top-of-stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations ? goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value ? 2013 microchip technology inc. preliminary ds40001684b-page 79 PIC16F570 table 13-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z none z none z z none none c c c, dc, z none z 1, 2, 4 2, 4 4 2, 4 2, 4 2, 4 2, 4 2, 4 2, 4 1, 4 2, 4 2, 4 1, 2, 4 2, 4 2, 4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2, 4 2, 4 literal and control operations andlw call clrwdt goto iorlw movlb movlw option retfie retlw return sleep tris xorlw k k ? k k k k ? ? k ? ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to bsr register move literal to w load option register return from interrupt return, place literal in w return, maintain w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 1 2 2 2 1 1 1 1110 1001 0000 101k 1101 0000 1100 0000 0000 1000 0000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk 0001 kkkk 0000 0001 kkkk 0001 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk 0kkk kkkk 0010 1111 kkkk 1110 0011 0fff kkkk z none to , pd none z none none none none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . see section 4.6 ?program counter? . 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 3: the instruction tris f , where f = 6, causes the contents of the w register to be written to the tri-state latches of porta. a ? 1 ? forces the pin to a high-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared (if assigned to tmr0). PIC16F570 ds40001684b-page 80 preliminary ? 2013 microchip technology inc. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 31 d ??? 0 ? 1 ? operation: (w) + (f) ? (dest) status affected: c, dc, z description: add the contents of the w register and register ?f?. if ?d? is? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w).and. (k) ? (w) status affected: z description: the contents of the w register are and?ed with the 8-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 31 d ?? [0,1] operation: (w) .and. (f) ? (dest) status affected: z description: the contents of the w register are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two-cycle instruction. ? 2013 microchip technology inc. preliminary ds40001684b-page 81 PIC16F570 btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 31 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. call subroutine call syntax: [ label ] call k operands: 0 ? k ? 255 operation: (pc) + 1 ? top-of-stack; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none description: subroutine call. first, return address (pc + 1) is pushed onto the stack. the 8-bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 31 operation: 00h ? (f); 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z description: the w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? to; 1 ? pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f ) ? (dest) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. PIC16F570 ds40001684b-page 82 preliminary ? 2013 microchip technology inc. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? (dest) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? d; skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. (k) ? (w) status affected: z description: the contents of the w register are or?ed with the 8-bit literal ?k?. the result is placed in the w register. ? 2013 microchip technology inc. preliminary ds40001684b-page 83 PIC16F570 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? (dest) status affected: z description: the contents of register ?f? are moved to destination ?d?. if ?d? is ? 0 ?, destination is the w register. if ?d? is ? 1 ?, the destination is file register ?f?. ?d? = 1 is useful as a test of a file register, since status flag z is affected. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 7 operation: k ? (bsr) status affected: none description: the 3-bit literal ?k? is loaded into the bsr register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the 8-bit literal ?k? is loaded into the w register. the ?don?t cares? will assembled as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 31 operation: (w) ? (f) status affected: none description: move data from the w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none description: the content of the w register is loaded into the option register. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc 1 ?? gie status affected: none description: the program counter is loaded from the top of the stack (the return address). gie bit of intcon0 is set. this is a two-cycle instruction. PIC16F570 ds40001684b-page 84 preliminary ? 2013 microchip technology inc. retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the 8-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: the program counter is loaded from the top of the stack (the return address). this is a two- cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated 1 bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. c register ?f? rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; 1 ? to ; 0 ? pd status affected: to , pd, rbwuf description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 8.10 ?power-down mode (sleep)? on sleep for more details. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 31 d ? [0,1] operation: (f) ? (w) ??? dest) status affected: c, dc, z description: subtract (2?s complement method) the w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. c register ?f? ? 2013 microchip technology inc. preliminary ds40001684b-page 85 PIC16F570 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) ? tris register f status affected: none description: tris register ?f? (f = 6, 7 or 8) is loaded with the contents of the w register xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the 8-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w) .xor. (f) ??? dest) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. PIC16F570 ds40001684b-page 86 preliminary ? 2013 microchip technology inc. ? 2013 microchip technology inc. preliminary ds40001684b-page 87 PIC16F570 14.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? x ide software ? compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab x sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 ? device programmers - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits and starter kits ? third-party development tools 14.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: ? color syntax highlighting ? smart code completion makes suggestions and provides hints as you type ? automatic code formatting based on user-defined rules ? live parsing user-friendly, customizable interface: ? fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. ? call graph window project-based workspaces: ? multiple projects ? multiple tools ? multiple configurations ? simultaneous debugging sessions file history and bug tracking: ? local file history feature ? built-in support for bugzilla issue tracker PIC16F570 ds40001684b-page 88 preliminary ? 2013 microchip technology inc. 14.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchip?s 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility 14.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: ? integration into mplab x ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multipurpose source files ? directives that allow complete control over the assembly process 14.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 14.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility ? 2013 microchip technology inc. preliminary ds40001684b-page 89 PIC16F570 14.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 14.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 14.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchip?s most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineer?s pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 14.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineer?s pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 14.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. PIC16F570 ds40001684b-page 90 preliminary ? 2013 microchip technology inc. 14.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 14.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. ? device programmers and gang programmers from companies, such as softlog and ccs ? software tools from companies, such as gimpel and trace systems ? protocol analyzers from companies, such as saleae and total phase ? demonstration boards from companies, such as mikroelektronika, digilent ? and olimex ? embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? ? 2013 microchip technology inc. preliminary ds40001684b-page 91 PIC16F570 15.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ......... -40c to +125c storage temperature ............................................................................................................ ................ -65c to +150c voltage on v dd with respect to v ss ............................................................................................................... 0 to +6.5v voltage on mclr with respect to v ss ..........................................................................................................0 to +13.5v voltage on all other pins with respect to v ss ............................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ... 700 mw max. current out of v ss pin ........................................................................................................................... ..... 200 ma max. current into v dd pin ........................................................................................................................... ........ 150 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????? 20 ma max. output current sunk by any i/o pin ........................................................................................ ...................... 25 ma max. output current sourced by any i/o pin ..................................................................................... .................... 25 ma max. output current sourced by i/o port ....................................................................................... ....................... 75 ma max. output current sunk by i/o port .......................................................................................... ......................... 75 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. PIC16F570 ds40001684b-page 92 preliminary ? 2013 microchip technology inc. figure 15-1: PIC16F570 volt age-frequency graph, -40 ? c ? t a ? +125 ? c figure 15-2: maximum oscillator frequency table 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 8 0 200 khz 4 mhz 20 mhz frequency hs intosc xt lp oscillator mode ec xtrc 8 mhz ? 2013 microchip technology inc. preliminary ds40001684b-page 93 PIC16F570 15.1 dc characteristics: PIC16F570 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) param. no. sym. characteristic min. typ. (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 15-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ?vsee section 8.5 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.5 ?power-on reset (por)? for details d005 i ddp supply current during prog/erase ? 1.0* ? ma v dd = 5.0v d010 i dd supply current (3,4,6) ? ? 175 490 300 750 ? a ? a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 350 850 500 1300 ? a ? a f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ? 1800 2300 ? af osc = 20 mhz, v dd = 5.0v ? ? 13 30 22 55 ? a ? a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 1.2 2.2 ? a ? a v dd = 2.0v v dd = 5.0v d021 i bor bor current (5) ? ? 3.5 4.0 7.0 9.0 ? a ? a v dd = 3.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 8.0 3.0 16.0 ? a ? a v dd = 2.0v v dd = 5.0v d023 i cmp comparator current (5) ? ? 15 60 26 78 ? a ? a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d024 i cvref c v ref current (5) ? ? 30 75 70 125 ? a ? a v dd = 2.0v (high range) v dd = 5.0v (high range) d025 i vfir internal 0.6v fixed voltage reference current (5) ? ? 100 175 125 205 ? a ? a v dd = 2.0v (reference and 1 comparator enabled) v dd = 5.0v (reference and 1 comparator enabled) d026 i ad 2 a/d current ? ? 0.5 0.8 2.0 3.0 ? a ? a 2.0v, no conversion in progress 5.0v, no conversion in progress d027 i opa op amp current (5) ? ? 280 310 370 420 ? a ? a v dd = 2.0v v dd = 5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k ? . PIC16F570 ds40001684b-page 94 preliminary ? 2013 microchip technology inc. 15.2 dc characteristics: PIC16F570 (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 40 ? c ? t a ? +125 ? c (extended) param. no. sym. characteristic min. typ. (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 15-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power- on reset ?v ss ? v see section 8.5 ?power-on reset (por)? for details. d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.5 ?power-on reset (por)? for details. d005 i ddp supply current during prog/erase ? 1.0* ? ma v dd = 5.0v d010 i dd supply current (3,4,6) ? ? 175 490 300 750 ? a ? a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 350 850 500 1300 ? a ? a f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ? 1800 2300 ? af osc = 20 mhz, v dd = 5.0v ? ? 13 30 26 110 ? a ? a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 9.0 15.0 ? a ? a v dd = 2.0v v dd = 5.0v d021 i bor bor current (5) ? ? 3.5 4.0 10 12 ? a ? a v dd = 3.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 8.0 18 22 ? a ? a v dd = 2.0v v dd = 5.0v d023 i cmp comparator current (5) ? ? 15 60 28 92 ? a ? a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d024 i cvref cv ref current (5) ? ? 30 75 75 135 ? a ? a v dd = 2.0v (high range) v dd = 5.0v (high range) d025 i vfir internal 0.6v fixed voltage reference current (5) ? ? 100 175 135 220 ? a ? a v dd = 2.0v (reference and 1 comparator enabled) v dd = 5.0v (reference and 1 comparator enabled) d026 i ad 2 a/d current ? ? 0.5 0.8 10.0 16.0 ? a ? a 2.0v, no conversion in progress 5.0v, no conversion in progress d027 i opa op amp current (5) ? ? 280 310 420 470 ? a ? a v dd = 2.0v v dd = 5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterizati on results at 25c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code executi on pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, t he conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k ? . ? 2013 microchip technology inc. preliminary ds40001684b-page 95 PIC16F570 table 15-1: dc characteristics: PIC16F570 (industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40c ? t a ? +85c (industrial) -40c ? t a ? +125c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ.? max. units conditions v il input low voltage i/o ports d030 with ttl buffer vss ? 0.8v v for all 4.5 ? v dd ?? 5.5v d030a vss ? 0.15v dd v otherwise d031 with schmitt trigger buffer vss ? 0.15v dd v d032 mclr , t0cki vss ? 0.15v dd v d033 osc1 (extrc mode), (ec mode) vss ? 0.15v dd v (note 1) d033 osc1 (hs mode) vss ? 0.3v dd v d033 osc1 (xt and lp modes) vss ? 0.3 v v ih input high voltage i/o ports ? d040 with ttl buffer 2.0 ? v dd v4.5 ? v dd ?? 5.5v d040a 0.25v dd + 0.8v dd ?v dd v otherwise d041 with schmitt trigger buffer 0.85v dd ?v dd v for entire v dd range d042 mclr , t0cki 0.85v dd ?v dd v d042a osc1 (extrc mode), (ec mode) 0.85v dd ?v dd v (note 1) d042a osc1 (hs mode) 0.7v dd ?v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v d070 i pur portb and mclr weak pull-up current (4) 50 250 400 ? av dd = 5v, v pin = v ss i il input leakage current (2,3) d060 i/o ports ? ? 1 ? a vss ?? v pin ?? v dd , pin at high-impedance d061 m clr ?0.75 ? a vss ?? v pin ?? v dd d063 osc1 ? ? 5 ? a vss ?? v pin ?? v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports/clkout ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 ? c to +85 ? c d080a ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 ? c to +125 ? c d083 osc2 ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 ? c to +85 ? c d083a ? ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 ? c to +125 ? c v oh output high voltage d090 i/o ports/clkout v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 ? c to +85 ? c d090a v dd ? 0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, -40 ? c to +125 ? c d092 osc2 v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 ? c to +85 ? c d092a v dd ? 0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, -40 ? c to +125 ? c ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the PIC16F570 be d riven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: this spec applies to all weak pull-up devices, including the weak pull-up found on m clr . PIC16F570 ds40001684b-page 96 preliminary ? 2013 microchip technology inc. capacitive loading specs on output pins d100 cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 cio all i/o pins and osc2 ? ? 50 pf flash data memory d120 e d byte endurance 100k 1m ? e/w -40 ? c ? t a ? +85 ? c d120a e d byte endurance 10k 100k ? e/w +85 ? c ? t a ? +125 ? c d121 v drw v dd for read/write v min ?5.5 v table 15-1: dc characteristics: PIC16F570 (industrial, extended) (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40c ? t a ? +85c (industrial) -40c ? t a ? +125c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ.? max. units conditions ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the PIC16F570 be d riven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: this spec applies to all weak pull-up devices, including the weak pull-up found on m clr . ? 2013 microchip technology inc. preliminary ds40001684b-page 97 PIC16F570 table 15-2: comparator specifications comparator specifications standard operating conditions (unless otherwise stated) operating temperature -40c to 125c characteristics sym. min. typ. max. units comments input offset voltage v os ? 5.0 10.0 mv input common mode voltage* v cm 0?v dd ? 1.5 v cmrr* c mrr 55 ? ? db response time (1)* t rt ?150 ? ns comparator mode change to output valid* t mc 2 cov ?? 10 ? s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd ? 1.5v. table 15-3: comparator voltage reference (cv ref ) specifications sym. characteristics min. typ. max. units comments cv res resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) absolute accuracy (2) ? ? ? ? 1/2* 1/2* lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) unit resistor value (r) ? ? 2k* ? ? settling time (1) ??10* ? s * these parameters are characterized but not tested. note 1: settling time measured while v rr = 1 and vr<3:0> transitions from 0000 to 1111 . 2: do not use reference externally when v dd < 2.7v. under this condition, reference should only be used with comparator voltage common mode observed. table 15-4: fixed input reference specification input reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c to 125c characteristics sym. min. typ. max. units comments absolute accuracy v fir 0.5 0.60 0.7 v PIC16F570 ds40001684b-page 98 preliminary ? 2013 microchip technology inc. table 15-5: a/d converter characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param. no. sym. characteristic min. typ.? max. units conditions a01 n r resolution ? ? 8 bit a03 e inl integral error ? ? ? 1.5 lsb v dd = 5.0v a04 e dnl differential error ? ? ????? e dnl ?? 1.7 lsb no missing codes v dd = 5.0v a05 e fs full scale range 2.0* ? 5.5* v a06 e off offset error ? ? ? 1.5 lsb v dd = 5.0v a07 e gn gain error -0.7 ? ? 2.2 lsb v dd = 5.0v a10 ? monotonicity ? guaranteed (1) ??v ss ? v ain ? v dd a25* v ain analog input voltage v ss ?v dd v a30* z ain recommended impedance of analog voltage source ?? 10k ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. ? 2013 microchip technology inc. preliminary ds40001684b-page 99 PIC16F570 15.3 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 15-3: load conditions figure 15-4: exter nal clock timing 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance c l v ss pin legend: c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 osc1 q4 q1 q2 q3 q4 q1 133 44 2 PIC16F570 ds40001684b-page 100 preliminary ? 2013 microchip technology inc. table 15-6: external clock timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial), -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ. (1) max. units conditions 1a f osc external clkin frequency (2) dc ? 4 mhz xt oscillator dc ? 20 mhz hs oscillator dc ? 200 khz lp oscillator oscillator frequency (2) dc ? 4 mhz extrc oscillator 0.1 ? 4 mhz xt oscillator 4 ? 20 mhz hs oscillator dc ? 200 khz lp oscillator 1t osc external clkin period (2) 250 ? ? ns xt oscillator 50 ? ? ns hs oscillator 5? ? ? s lp oscillator oscillator period (2) 250 ? ? ns extrc oscillator 250 ? 10,000 ns xt oscillator 50 ? 250 ns hs oscillator 5? ? ? s lp oscillator 2 t cy instruction cycle time 200 4/f osc dc ns 3 tosl, to s h clock in (osc1) low or high time 50* ? ? ns xt oscillator 2* ? ? ? s lp oscillator 10* ? ? ns hs oscillator 4tosr, to s f clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 50* ns lp oscillator ? ? 15* ns hs oscillator * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. ? 2013 microchip technology inc. preliminary ds40001684b-page 101 PIC16F570 table 15-7: calibrated internal rc frequencies ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial), -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic freq. tolerance min. typ.? max. units conditions f10 f osc internal calibrated intosc frequency (1) ? 1% 7.92 8.00 8.08 mhz 3.5v, 25c ? 2% 7.84 8.00 8.16 mhz 2.5v ?? v dd ? 5.5v 0 ? c ? t a ? +85 ? c ? 5% 7.60 8.00 8.40 mhz 2.0v ?? v dd ? 5.5v -40 ? c ? t a ? +85 ? c (ind.) -40 ? c ? t a ? +125 ? c (ext.) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 uf and 0.01 uf values in parallel are recommended. PIC16F570 ds40001684b-page 102 preliminary ? 2013 microchip technology inc. figure 15-5: i/o timing osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value 19 note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. table 15-8: timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ. (1) max. units 17 t os h2 io vosc1 ? (q1 cycle) to port out valid (2,3) ? ? 100* ns 18 t os h2 io iosc1 ? (q2 cycle) to port input invalid (i/o in hold time) (2) 50* ? ? ns 19 t io v2 os h port input valid to osc1 ? (i/o in setup time) 20* ? ? ns 20 t io r port output rise time (3) ?1050**ns 21 t io f port output fall time (3) ?1050**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 15-3 for loading conditions. ? 2013 microchip technology inc. preliminary ds40001684b-page 103 PIC16F570 figure 15-6: reset, watchdog timer and device reset timer timing figure 15-7: brown-out rese t timing and characteristics v dd mclr internal por drt time-out (2) internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: i/o pins must be taken out of high-impedance mode by enabling the output drivers in software. 2: runs in mclr or wdt reset only in xt, lp and hs modes. v bor v dd (device in brown-out reset) (device not in brown-out reset) t bor reset (due to bor) v bor + v hyst t drt PIC16F570 ds40001684b-page 104 preliminary ? 2013 microchip technology inc. table 15-9: bor, por, watchdog timer and device reset timer ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ. (1) max. units conditions 30 t mc lmclr pulse width (low) 2000* ? ? ns v dd = 5.0v 31 t wdt watchdog timer time-out period (no prescaler) 9* 9* 18* 18 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 32 t drt device reset timer period 9* 9* 18* 18 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 34 t ioz i/o high-impedance from mclr low ? ? 2000* ns 35 v bor brown-out reset voltage 1.95 ? 2.25 v (note 2) 36* v hyst brown-out reset hysteresis ? 50 ? mv 37* t bor brown-out reset minimum detection period 100 ? ? ? sv dd ? v bor * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. table 15-10: drt (device reset timer period) oscillator configuration por reset subsequent resets intrc, extrc, and ec 10 ? s (typical) + 18 ms (drten = 1 )10 ? s (typical) + 18 ms (drten = 1 ) xt, hs and lp 18 ms (typical) 18 ms (typical) table 15-11: pull-up resistor ranges v dd (volts) temperature ( ? c) min. typ. max. units rb0-rb7 2.0 -40 73k 105k 186k ? 25 73k 113k 187k ? 85 82k 123k 190k ? 125 86k 132k 190k ? 5.5 -40 15k 21k 33k ? 25 15k 22k 34k ? 85 19k 26k 35k ? 125 23k 29k 35k ? mclr 2.0 -40 63k 81k 96k ? 25 77k 93k 116k ? 85 82k 96k 116k ? 125 86k 100k 119k ? 5.5 -40 16k 20k 22k ? 25 16k 21k 23k ? 85 24k 25k 28k ? 125 26k 27k 29k ? ? 2013 microchip technology inc. preliminary ds40001684b-page 105 PIC16F570 figure 15-8: timer0 clock timings t0cki 40 41 42 table 15-12: timer0 clock requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ. (1) max. units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40* n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are char acterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. PIC16F570 ds40001684b-page 106 preliminary ? 2013 microchip technology inc. 15.4 operational amplifiers table 15-13: operational amplifier (opa) modu le dc specifications opa dc characteristics standard operating conditions (unless otherwise stated) v dd = 5.0v operating temperature : 25c param. no. sym. characteristics min. typ. max. units comments opa01 v os input offset voltage ? ? 510mv opa02* opa03* i b i os input current and impedance input bias current input offset bias current ? ? ? 2* ? 1* ? ? na pa opa04* opa05* v cm cmr common mode common mode input range common mode rejection v ss 55 ? 65 v dd ? 1.4 ? v db opa06a* opa06b* a ol a ol open loop gain dc open loop gain dc open loop gain ? ? 90 60 ? ? db db no load standard load opa07* opa08* v out i sc output output voltage swing output short circuit current v ss + 50 ? ? 25 v dd ? 50 28 mv ma to v dd /2 (20 k ? connected to v dd , 20 k ? + 20 pf to vss) opa10* psr power supply power supply rejection 80 ? ? db * these parameters are characterized but not tested. table 15-14: ac characteristics: operational amplifier (opa) ac characteristics standard operating conditions (unless otherwise stated) operating temperature: 25c v dd = 5.0v param. no. parameters symbol min. typ. max. units conditions opa12* gain bandwidth product gbwp ? 3 ? mhz v dd = 5v opa13* turn on time t on ?? 10 sv dd = 5v opa14* phase margin ? m ? 60 ? degrees v dd = 5v opa15* slew rate sr 2 ? ? v/s v dd = 5v * these parameters are characterized but not tested. note 1: data in ?typ? column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. ? 2013 microchip technology inc. preliminary ds40001684b-page 107 PIC16F570 table 15-15: flash data memory write/erase time ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 15.1 ?dc characteristics: PIC16F570 (industrial)? . param. no. sym. characteristic min. typ. (1) max. units conditions 43 t dw flash data memory write cycle time 23.55ms 44 t de flash data memory erase cycle time 23.55ms note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. PIC16F570 ds40001684b-page 108 preliminary ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. preliminary ds40001684b-page 109 PIC16F570 16.0 dc and ac characteristics graphs and charts graphs and tables are not available at this time. PIC16F570 ds40001684b-page 110 preliminary ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. preliminary ds40001684b-page 111 PIC16F570 17.0 packaging information 17.1 package marking information * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead spdip (.300?) example 1304017 -i/sp 3 e PIC16F570 28-lead soic (7.50 mm) example yywwnnn xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx e PIC16F570 -i/so 1304017 PIC16F570 ds40001684b-page 112 preliminary ? 2013 microchip technology inc. package marking information (continued) * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead ssop (5.30 mm) example PIC16F570 1304017 -i/ss 3 e 28-lead uqfn (4x4x0.5 mm) example pin 1 pin 1 pi1 1 i 3 e 28-lead qfn (6x6 mm) example xxxxxxxx xxxxxxxx yywwnnn pin 1 pin 1 16f570 1304017 i/ml 3 e ? 2013 microchip technology inc. preliminary ds40001684b-page 113 PIC16F570 ! " !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! ! " 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - -- ## 4 >#& . < : 9& - -? & & 9 - 9 # 4!! < 6 9 #>#& ) 9 * 9 #>#& ) < : * + 1 = = - note 1 n 12 d e1 eb c e l a2 e b b1 a1 a 3 * ,1 PIC16F570 ds40001684b-page 114 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. preliminary ds40001684b-page 115 PIC16F570 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging PIC16F570 ds40001684b-page 116 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. preliminary ds40001684b-page 117 PIC16F570 #$ % &' % ! " !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$#'' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! ! " 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! ? < & # %% = = : >#& . < < ## 4 >#& . - ? : 9& 3 &9& 9 3 & & 9 .3 9 # 4!! = 3 & @ @ <@ 9 #>#& ) = -< l l1 c a2 a1 a e e1 d n 1 2 note 1 b e * ,-1 PIC16F570 ds40001684b-page 118 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. preliminary ds40001684b-page 119 PIC16F570 PIC16F570 ds40001684b-page 120 preliminary ? 2013 microchip technology inc. ? 2013 microchip technology inc. preliminary ds40001684b-page 121 PIC16F570 ( )* ! + , -.- ()! / # '&& 0 +# ! " 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 PIC16F570 ds40001684b-page 122 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. preliminary ds40001684b-page 123 PIC16F570 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging PIC16F570 ds40001684b-page 124 preliminary ? 2013 microchip technology inc. ? 2013 microchip technology inc. preliminary ds40001684b-page 125 PIC16F570 appendix a: data sheet revision history revision a (02/2013) initial release of this document. revision b (05/2013) updated the family types table (table 1); updated figure 3-1; updated the memory organization section; updated examples 5-1, 5-2 and 5-3; updated figure 6-1; updated note 1 in register 6-5; updated register 8-1; updated figure 8-6; added new section 9.1.5, a/d acquisition requirements; updated register 9-1; updated figure 10-1 and register 10-1; updated section 12, opa module; updated the electrical specifications section; other minor corrections. PIC16F570 ds40001684b-page 126 preliminary ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. preliminary ds40001684b-page 127 PIC16F570 index a adc internal sampling switch (r ss ) i mpedance ................ 61 source impedance...................................................... 61 alu ....................................................................................... 9 analog-to-digital (a/d) converter ....................................... 61 architectural overview .......................................................... 9 assembler mpasm assembler..................................................... 86 b block diagram on-chip reset circuit ................................................. 50 timer0......................................................................... 37 tmr0/wdt prescaler................................................. 41 watchdog timer.......................................................... 53 block diagrams analog input model ..................................................... 62 opa module................................................................ 75 c c compilers mplab c18 ................................................................ 86 carry ..................................................................................... 9 clock divisors ..................................................................... 61 clocking scheme ................................................................ 13 cmos technology................................................................ 1 code protection ............................................................ 30, 43 comparator voltage reference module ............................. 73 comparator(s)..................................................................... 67 config register................................................................ 44 configuration bits................................................................ 43 customer change notification service ............................. 127 customer support............................................................. 127 d dc and ac characteristics ............................................... 107 graphs and tables ................................................... 107 development support ......................................................... 85 digit carry ............................................................................. 9 e effects of reset opa module................................................................ 76 electrical characteristics..................................................... 89 errata .................................................................................... 4 f fsr ..................................................................................... 24 i i/o interfacing ..................................................................... 32 i/o port................................................................................ 31 i/o programming considerations........................................ 35 id locations .................................................................. 43, 59 indf.................................................................................... 24 indirect data addressing..................................................... 24 instruction cycle ................................................................. 13 instruction flow/pipelining .................................................. 13 instruction set summary..................................................... 78 internal sampling switch (r ss ) i mpedance ........................ 61 internet address................................................................ 127 l loading of pc ..................................................................... 23 m memory organization ......................................................... 15 memory map............................................................... 15 PIC16F570 ................................................................. 15 program memory (PIC16F570) .................................. 15 microchip internet web site.............................................. 127 microcontroller features ....................................................... 1 mplab asm30 assembler, linker, librarian ..................... 86 mplab integrated development environment software.... 85 mplab pm3 device programmer ...................................... 87 mplab real ice in-circuit emulator system .................. 87 mplink object linker/mplib object librarian .................. 86 o operational amplifier (opa) module .................................. 75 associated registers.................................................. 76 option register................................................................ 21 osc selection..................................................................... 43 osccal register............................................................... 22 oscillator configurations..................................................... 45 oscillator types ec............................................................................... 45 extrc ....................................................................... 45 hs............................................................................... 45 intrc......................................................................... 45 lp ............................................................................... 45 xt ............................................................................... 45 p peripheral features .............................................................. 1 PIC16F570 device varieties................................................. 7 PIC16F570 register file map ............................................ 17 por device reset timer (drt) ................................... 43, 52 pd ............................................................................... 53 power-on reset (por)............................................... 43 to ............................................................................... 53 porta ............................................................................... 31 portb ............................................................................... 31 portc ............................................................................... 31 power-down mode.............................................................. 55 prescaler ............................................................................ 40 processor features .............................................................. 1 program counter ................................................................ 23 q q cycles .............................................................................. 13 r reader response............................................................. 128 reading flash data memory .............................................. 27 register definitions ? memory control ............................. 29 registers config (configuration word register) ..................... 44 special function ......................................................... 16 reset .................................................................................. 43 revision history................................................................ 123 s self-writable flash data memory control .......................... 27 sleep ............................................................................ 43, 55 PIC16F570 ds40001684b-page 128 preliminary ? 2013 microchip technology inc. software simulator (mplab sim)....................................... 87 special features of the cpu............................................... 43 special function registers ................................................. 16 stack ................................................................................... 23 status register................................................................ 20 status register ................................................................. 53 status register...................................................................... 9 t timer0 timer0 (tmr0) module ............................................... 37 tmr0 with external clock........................................... 39 timing diagrams brown-out reset situations ........................................ 54 timing parameter symbology and load conditions........... 97 tris register...................................................................... 31 w wake-up from sleep ........................................................... 55 watchdog timer (wdt) ................................................ 43, 52 period.......................................................................... 52 programming considerations ..................................... 52 write/verify.......................................................................... 28 www address.................................................................. 127 www, on-line support........................................................ 4 z zero bit .................................................................................. 9 ? 2013 microchip technology inc. preliminary ds40001684b-page 129 PIC16F570 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: ? product support ? data sheets and errata, appli- cation notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?cus- tomer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support PIC16F570 ds40001684b-page 130 preliminary ? 2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40001684b PIC16F570 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2013 microchip technology inc. preliminary ds40001684b-page 131 PIC16F570 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: PIC16F570 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c (industrial) e= -40 ? c to +125 ? c (extended) package: ml = micro lead frame (qfn) 6x6 mv = micro lead frame (uqfn) 4x4 sp = skinny plastic dip (spdip) s0 = small outline (7.50 mm) (soic) ss = shrink small outline (5.30 mm) (ssop) pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) PIC16F570t - i/ml 301 tape and reel, industrial temperature, qfn 6x6 package, qtp pattern #301 b) PIC16F570 - e/sp extended temperature spdip package c) PIC16F570 - e/so extended temperature, soic package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. [x] (1) tape and reel option - PIC16F570 ds40001684b-page 132 preliminary ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. preliminary ds40001684b-page 133 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620772157 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds40001684b-page 134 preliminary ? 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